RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00
Code Issues Projects Releases Wiki Activity

[CodeGen] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).

Browse Source 
llvm-svn: 295893
This commit is contained in:
Eugene Zelenko 2017-02-22 22:32:51 +00:00
parent 578d2eb656
commit 8c806a2ad0
13 changed files with 382 additions and 284 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

97
include/llvm/CodeGen/MachineScheduler.h
View File

@ -1,4 +1,4 @@
//==- MachineScheduler.h - MachineInstr Scheduling Pass ----------*- C++ -*-==//
//===- MachineScheduler.h - MachineInstr Scheduling Pass --------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -112,12 +112,12 @@ class ScheduleHazardRecognizer;
/// MachineSchedContext provides enough context from the MachineScheduler pass
/// for the target to instantiate a scheduler.
struct MachineSchedContext {
MachineFunction *MF;
const MachineLoopInfo *MLI;
const MachineDominatorTree *MDT;
const TargetPassConfig *PassConfig;
AliasAnalysis *AA;
LiveIntervals *LIS;
MachineFunction *MF = nullptr;
const MachineLoopInfo *MLI = nullptr;
const MachineDominatorTree *MDT = nullptr;
const TargetPassConfig *PassConfig = nullptr;
AliasAnalysis *AA = nullptr;
LiveIntervals *LIS = nullptr;
RegisterClassInfo *RegClassInfo;
@ -165,22 +165,21 @@ class ScheduleDAGMI;
/// before building the DAG.
struct MachineSchedPolicy {
// Allow the scheduler to disable register pressure tracking.
bool ShouldTrackPressure;
bool ShouldTrackPressure = false;
/// Track LaneMasks to allow reordering of independent subregister writes
/// of the same vreg. \sa MachineSchedStrategy::shouldTrackLaneMasks()
bool ShouldTrackLaneMasks;
bool ShouldTrackLaneMasks = false;
// Allow the scheduler to force top-down or bottom-up scheduling. If neither
// is true, the scheduler runs in both directions and converges.
bool OnlyTopDown;
bool OnlyBottomUp;
bool OnlyTopDown = false;
bool OnlyBottomUp = false;
// Disable heuristic that tries to fetch nodes from long dependency chains
// first.
bool DisableLatencyHeuristic;
bool DisableLatencyHeuristic = false;
MachineSchedPolicy(): ShouldTrackPressure(false), ShouldTrackLaneMasks(false),
OnlyTopDown(false), OnlyBottomUp(false), DisableLatencyHeuristic(false) {}
MachineSchedPolicy() = default;
};
/// MachineSchedStrategy - Interface to the scheduling algorithm used by
@ -232,6 +231,7 @@ public:
/// When all predecessor dependencies have been resolved, free this node for
/// top-down scheduling.
virtual void releaseTopNode(SUnit *SU) = 0;
/// When all successor dependencies have been resolved, free this node for
/// bottom-up scheduling.
virtual void releaseBottomNode(SUnit *SU) = 0;
@ -261,24 +261,20 @@ protected:
MachineBasicBlock::iterator CurrentBottom;
/// Record the next node in a scheduled cluster.
const SUnit *NextClusterPred;
const SUnit *NextClusterSucc;
const SUnit *NextClusterPred = nullptr;
const SUnit *NextClusterSucc = nullptr;
#ifndef NDEBUG
/// The number of instructions scheduled so far. Used to cut off the
/// scheduler at the point determined by misched-cutoff.
unsigned NumInstrsScheduled;
unsigned NumInstrsScheduled = 0;
#endif
public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool RemoveKillFlags)
: ScheduleDAGInstrs(*C->MF, C->MLI, RemoveKillFlags), AA(C->AA),
LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU),
NextClusterPred(nullptr), NextClusterSucc(nullptr) {
#ifndef NDEBUG
NumInstrsScheduled = 0;
#endif
}
LIS(C->LIS), SchedImpl(std::move(S)), Topo(SUnits, &ExitSU) {}
// Provide a vtable anchor
~ScheduleDAGMI() override;
@ -375,7 +371,7 @@ protected:
/// Information about DAG subtrees. If DFSResult is NULL, then SchedulerTrees
/// will be empty.
SchedDFSResult *DFSResult;
SchedDFSResult *DFSResult = nullptr;
BitVector ScheduledTrees;
MachineBasicBlock::iterator LiveRegionEnd;
@ -389,8 +385,8 @@ protected:
PressureDiffs SUPressureDiffs;
/// Register pressure in this region computed by initRegPressure.
bool ShouldTrackPressure;
bool ShouldTrackLaneMasks;
bool ShouldTrackPressure = false;
bool ShouldTrackLaneMasks = false;
IntervalPressure RegPressure;
RegPressureTracker RPTracker;
@ -409,16 +405,14 @@ protected:
/// True if disconnected subregister components are already renamed.
/// The renaming is only done on demand if lane masks are tracked.
bool DisconnectedComponentsRenamed;
bool DisconnectedComponentsRenamed = false;
public:
ScheduleDAGMILive(MachineSchedContext *C,
std::unique_ptr<MachineSchedStrategy> S)
: ScheduleDAGMI(C, std::move(S), /*RemoveKillFlags=*/false),
RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
ShouldTrackPressure(false), ShouldTrackLaneMasks(false),
RPTracker(RegPressure), TopRPTracker(TopPressure),
BotRPTracker(BotPressure), DisconnectedComponentsRenamed(false) {}
RegClassInfo(C->RegClassInfo), RPTracker(RegPressure),
TopRPTracker(TopPressure), BotRPTracker(BotPressure) {}
~ScheduleDAGMILive() override;
@ -573,6 +567,8 @@ struct SchedRemainder {
// Unscheduled resources
SmallVector<unsigned, 16> RemainingCounts;
SchedRemainder() { reset(); }
void reset() {
CriticalPath = 0;
CyclicCritPath = 0;
@ -581,8 +577,6 @@ struct SchedRemainder {
RemainingCounts.clear();
}
SchedRemainder() { reset(); }
void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
};
@ -598,14 +592,14 @@ public:
LogMaxQID = 2
};
ScheduleDAGMI *DAG;
const TargetSchedModel *SchedModel;
SchedRemainder *Rem;
ScheduleDAGMI *DAG = nullptr;
const TargetSchedModel *SchedModel = nullptr;
SchedRemainder *Rem = nullptr;
ReadyQueue Available;
ReadyQueue Pending;
ScheduleHazardRecognizer *HazardRec;
ScheduleHazardRecognizer *HazardRec = nullptr;
private:
/// True if the pending Q should be checked/updated before scheduling another
@ -665,9 +659,7 @@ public:
/// Pending queues extend the ready queues with the same ID and the
/// PendingFlag set.
SchedBoundary(unsigned ID, const Twine &Name):
DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
Pending(ID << LogMaxQID, Name+".P"),
HazardRec(nullptr) {
Available(ID, Name+".A"), Pending(ID << LogMaxQID, Name+".P") {
reset();
}
@ -781,11 +773,11 @@ public:
/// Policy for scheduling the next instruction in the candidate's zone.
struct CandPolicy {
bool ReduceLatency;
unsigned ReduceResIdx;
unsigned DemandResIdx;
bool ReduceLatency = false;
unsigned ReduceResIdx = 0;
unsigned DemandResIdx = 0;
CandPolicy(): ReduceLatency(false), ReduceResIdx(0), DemandResIdx(0) {}
CandPolicy() = default;
bool operator==(const CandPolicy &RHS) const {
return ReduceLatency == RHS.ReduceLatency &&
@ -800,12 +792,12 @@ public:
/// Status of an instruction's critical resource consumption.
struct SchedResourceDelta {
// Count critical resources in the scheduled region required by SU.
unsigned CritResources;
unsigned CritResources = 0;
// Count critical resources from another region consumed by SU.
unsigned DemandedResources;
unsigned DemandedResources = 0;
SchedResourceDelta(): CritResources(0), DemandedResources(0) {}
SchedResourceDelta() = default;
bool operator==(const SchedResourceDelta &RHS) const {
return CritResources == RHS.CritResources
@ -866,13 +858,12 @@ public:
protected:
const MachineSchedContext *Context;
const TargetSchedModel *SchedModel;
const TargetRegisterInfo *TRI;
const TargetSchedModel *SchedModel = nullptr;
const TargetRegisterInfo *TRI = nullptr;
SchedRemainder Rem;
GenericSchedulerBase(const MachineSchedContext *C):
Context(C), SchedModel(nullptr), TRI(nullptr) {}
GenericSchedulerBase(const MachineSchedContext *C) : Context(C) {}
void setPolicy(CandPolicy &Policy, bool IsPostRA, SchedBoundary &CurrZone,
SchedBoundary *OtherZone);
@ -887,7 +878,7 @@ protected:
class GenericScheduler : public GenericSchedulerBase {
public:
GenericScheduler(const MachineSchedContext *C):
GenericSchedulerBase(C), DAG(nullptr), Top(SchedBoundary::TopQID, "TopQ"),
GenericSchedulerBase(C), Top(SchedBoundary::TopQID, "TopQ"),
Bot(SchedBoundary::BotQID, "BotQ") {}
void initPolicy(MachineBasicBlock::iterator Begin,
@ -929,7 +920,7 @@ public:
void registerRoots() override;
protected:
ScheduleDAGMILive *DAG;
ScheduleDAGMILive *DAG = nullptr;
MachineSchedPolicy RegionPolicy;

185
include/llvm/CodeGen/ScheduleDAG.h
View File

@ -1,4 +1,4 @@
//===------- llvm/CodeGen/ScheduleDAG.h - Common Base Class------*- C++ -*-===//
//===- llvm/CodeGen/ScheduleDAG.h - Common Base Class -----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -18,27 +18,32 @@
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/GraphTraits.h"
#include "llvm/ADT/iterator.h"
#include "llvm/ADT/PointerIntPair.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetLowering.h"
#include <cassert>
#include <cstddef>
#include <iterator>
#include <string>
#include <vector>
namespace llvm {
class SUnit;
class MachineConstantPool;
class MachineFunction;
class MachineRegisterInfo;
class MachineInstr;
struct MCSchedClassDesc;
class TargetRegisterInfo;
class ScheduleDAG;
class SDNode;
class TargetInstrInfo;
class MCInstrDesc;
class TargetMachine;
class TargetRegisterClass;
template<class Graph> class GraphWriter;
template<class Graph> class GraphWriter;
class MachineFunction;
class MachineRegisterInfo;
class MCInstrDesc;
struct MCSchedClassDesc;
class ScheduleDAG;
class SDNode;
class SUnit;
class TargetInstrInfo;
class TargetMachine;
class TargetRegisterClass;
class TargetRegisterInfo;
/// Scheduling dependency. This represents one direction of an edge in the
/// scheduling DAG.
@ -115,6 +120,7 @@ namespace llvm {
break;
}
}
SDep(SUnit *S, OrderKind kind)
: Dep(S, Order), Contents(), Latency(0) {
Contents.OrdKind = kind;
@ -239,14 +245,15 @@ namespace llvm {
private:
enum : unsigned { BoundaryID = ~0u };
SDNode *Node; ///< Representative node.
MachineInstr *Instr; ///< Alternatively, a MachineInstr.
public:
SUnit *OrigNode; ///< If not this, the node from which
/// this node was cloned.
/// (SD scheduling only)
SDNode *Node = nullptr; ///< Representative node.
MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
const MCSchedClassDesc *SchedClass; ///< nullptr or resolved SchedClass.
public:
SUnit *OrigNode = nullptr; ///< If not this, the node from which this node
/// was cloned. (SD scheduling only)
const MCSchedClassDesc *SchedClass =
nullptr; ///< nullptr or resolved SchedClass.
SmallVector<SDep, 4> Preds; ///< All sunit predecessors.
SmallVector<SDep, 4> Succs; ///< All sunit successors.
@ -256,92 +263,78 @@ namespace llvm {
typedef SmallVectorImpl<SDep>::const_iterator const_pred_iterator;
typedef SmallVectorImpl<SDep>::const_iterator const_succ_iterator;
unsigned NodeNum; ///< Entry # of node in the node vector.
unsigned NodeQueueId; ///< Queue id of node.
unsigned NumPreds; ///< # of SDep::Data preds.
unsigned NumSuccs; ///< # of SDep::Data sucss.
unsigned NumPredsLeft; ///< # of preds not scheduled.
unsigned NumSuccsLeft; ///< # of succs not scheduled.
unsigned WeakPredsLeft; ///< # of weak preds not scheduled.
unsigned WeakSuccsLeft; ///< # of weak succs not scheduled.
unsigned short NumRegDefsLeft; ///< # of reg defs with no scheduled use.
unsigned short Latency; ///< Node latency.
bool isVRegCycle : 1; ///< May use and def the same vreg.
bool isCall : 1; ///< Is a function call.
bool isCallOp : 1; ///< Is a function call operand.
bool isTwoAddress : 1; ///< Is a two-address instruction.
bool isCommutable : 1; ///< Is a commutable instruction.
bool hasPhysRegUses : 1; ///< Has physreg uses.
bool hasPhysRegDefs : 1; ///< Has physreg defs that are being used.
bool hasPhysRegClobbers : 1; ///< Has any physreg defs, used or not.
bool isPending : 1; ///< True once pending.
bool isAvailable : 1; ///< True once available.
bool isScheduled : 1; ///< True once scheduled.
bool isScheduleHigh : 1; ///< True if preferable to schedule high.
bool isScheduleLow : 1; ///< True if preferable to schedule low.
bool isCloned : 1; ///< True if this node has been cloned.
bool isUnbuffered : 1; ///< Uses an unbuffered resource.
bool hasReservedResource : 1; ///< Uses a reserved resource.
Sched::Preference SchedulingPref; ///< Scheduling preference.
unsigned NodeNum = BoundaryID; ///< Entry # of node in the node vector.
unsigned NodeQueueId = 0; ///< Queue id of node.
unsigned NumPreds = 0; ///< # of SDep::Data preds.
unsigned NumSuccs = 0; ///< # of SDep::Data sucss.
unsigned NumPredsLeft = 0; ///< # of preds not scheduled.
unsigned NumSuccsLeft = 0; ///< # of succs not scheduled.
unsigned WeakPredsLeft = 0; ///< # of weak preds not scheduled.
unsigned WeakSuccsLeft = 0; ///< # of weak succs not scheduled.
unsigned short NumRegDefsLeft = 0; ///< # of reg defs with no scheduled use.
unsigned short Latency = 0; ///< Node latency.
bool isVRegCycle : 1; ///< May use and def the same vreg.
bool isCall : 1; ///< Is a function call.
bool isCallOp : 1; ///< Is a function call operand.
bool isTwoAddress : 1; ///< Is a two-address instruction.
bool isCommutable : 1; ///< Is a commutable instruction.
bool hasPhysRegUses : 1; ///< Has physreg uses.
bool hasPhysRegDefs : 1; ///< Has physreg defs that are being used.
bool hasPhysRegClobbers : 1; ///< Has any physreg defs, used or not.
bool isPending : 1; ///< True once pending.
bool isAvailable : 1; ///< True once available.
bool isScheduled : 1; ///< True once scheduled.
bool isScheduleHigh : 1; ///< True if preferable to schedule high.
bool isScheduleLow : 1; ///< True if preferable to schedule low.
bool isCloned : 1; ///< True if this node has been cloned.
bool isUnbuffered : 1; ///< Uses an unbuffered resource.
bool hasReservedResource : 1; ///< Uses a reserved resource.
Sched::Preference SchedulingPref = Sched::None; ///< Scheduling preference.
private:
bool isDepthCurrent : 1; ///< True if Depth is current.
bool isHeightCurrent : 1; ///< True if Height is current.
unsigned Depth; ///< Node depth.
unsigned Height; ///< Node height.
public:
unsigned TopReadyCycle; ///< Cycle relative to start when node is ready.
unsigned BotReadyCycle; ///< Cycle relative to end when node is ready.
bool isDepthCurrent : 1; ///< True if Depth is current.
bool isHeightCurrent : 1; ///< True if Height is current.
unsigned Depth = 0; ///< Node depth.
unsigned Height = 0; ///< Node height.
const TargetRegisterClass *CopyDstRC; ///< Is a special copy node if !=null.
const TargetRegisterClass *CopySrcRC;
public:
unsigned TopReadyCycle = 0; ///< Cycle relative to start when node is ready.
unsigned BotReadyCycle = 0; ///< Cycle relative to end when node is ready.
const TargetRegisterClass *CopyDstRC =
nullptr; ///< Is a special copy node if != nullptr.
const TargetRegisterClass *CopySrcRC = nullptr;
/// \brief Constructs an SUnit for pre-regalloc scheduling to represent an
/// SDNode and any nodes flagged to it.
SUnit(SDNode *node, unsigned nodenum)
: Node(node), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
NumPredsLeft(0), NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0),
NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
: Node(node), NodeNum(nodenum), isVRegCycle(false), isCall(false),
isCallOp(false), isTwoAddress(false), isCommutable(false),
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
isUnbuffered(false), hasReservedResource(false),
SchedulingPref(Sched::None), isDepthCurrent(false),
isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
isUnbuffered(false), hasReservedResource(false), isDepthCurrent(false),
isHeightCurrent(false) {}
/// \brief Constructs an SUnit for post-regalloc scheduling to represent a
/// MachineInstr.
SUnit(MachineInstr *instr, unsigned nodenum)
: Node(nullptr), Instr(instr), OrigNode(nullptr), SchedClass(nullptr),
NodeNum(nodenum), NodeQueueId(0), NumPreds(0), NumSuccs(0),
NumPredsLeft(0), NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0),
NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
: Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
isCallOp(false), isTwoAddress(false), isCommutable(false),
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
isUnbuffered(false), hasReservedResource(false),
SchedulingPref(Sched::None), isDepthCurrent(false),
isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
isUnbuffered(false), hasReservedResource(false), isDepthCurrent(false),
isHeightCurrent(false) {}
/// \brief Constructs a placeholder SUnit.
SUnit()
: Node(nullptr), Instr(nullptr), OrigNode(nullptr), SchedClass(nullptr),
NodeNum(BoundaryID), NodeQueueId(0), NumPreds(0), NumSuccs(0),
NumPredsLeft(0), NumSuccsLeft(0), WeakPredsLeft(0), WeakSuccsLeft(0),
NumRegDefsLeft(0), Latency(0), isVRegCycle(false), isCall(false),
isCallOp(false), isTwoAddress(false), isCommutable(false),
hasPhysRegUses(false), hasPhysRegDefs(false), hasPhysRegClobbers(false),
isPending(false), isAvailable(false), isScheduled(false),
isScheduleHigh(false), isScheduleLow(false), isCloned(false),
isUnbuffered(false), hasReservedResource(false),
SchedulingPref(Sched::None), isDepthCurrent(false),
isHeightCurrent(false), Depth(0), Height(0), TopReadyCycle(0),
BotReadyCycle(0), CopyDstRC(nullptr), CopySrcRC(nullptr) {}
: isVRegCycle(false), isCall(false), isCallOp(false), isTwoAddress(false),
isCommutable(false), hasPhysRegUses(false), hasPhysRegDefs(false),
hasPhysRegClobbers(false), isPending(false), isAvailable(false),
isScheduled(false), isScheduleHigh(false), isScheduleLow(false),
isCloned(false), isUnbuffered(false), hasReservedResource(false),
isDepthCurrent(false), isHeightCurrent(false) {}
/// \brief Boundary nodes are placeholders for the boundary of the
/// scheduling region.
@ -506,12 +499,14 @@ namespace llvm {
/// decide.
class SchedulingPriorityQueue {
virtual void anchor();
unsigned CurCycle;
unsigned CurCycle = 0;
bool HasReadyFilter;
public:
SchedulingPriorityQueue(bool rf = false):
CurCycle(0), HasReadyFilter(rf) {}
virtual ~SchedulingPriorityQueue() {}
SchedulingPriorityQueue(bool rf = false) : HasReadyFilter(rf) {}
virtual ~SchedulingPriorityQueue() = default;
virtual bool isBottomUp() const = 0;
@ -530,6 +525,7 @@ namespace llvm {
assert(!HasReadyFilter && "The ready filter must override isReady()");
return true;
}
virtual void push(SUnit *U) = 0;
void push_all(const std::vector<SUnit *> &Nodes) {
@ -623,6 +619,7 @@ namespace llvm {
unsigned Operand;
SUnitIterator(SUnit *N, unsigned Op) : Node(N), Operand(Op) {}
public:
bool operator==(const SUnitIterator& x) const {
return Operand == x.Operand;
@ -649,6 +646,7 @@ namespace llvm {
unsigned getOperand() const { return Operand; }
const SUnit *getNode() const { return Node; }
/// Tests if this is not an SDep::Data dependence.
bool isCtrlDep() const {
return getSDep().isCtrl();
@ -746,6 +744,7 @@ namespace llvm {
reverse_iterator rend() { return Index2Node.rend(); }
const_reverse_iterator rend() const { return Index2Node.rend(); }
};
}
#endif
} // end namespace llvm
#endif // LLVM_CODEGEN_SCHEDULEDAG_H

25
include/llvm/CodeGen/ScheduleDAGMutation.h
View File

@ -1,4 +1,4 @@
//==- ScheduleDAGMutation.h - MachineInstr Scheduling ------------*- C++ -*-==//
//===- ScheduleDAGMutation.h - MachineInstr Scheduling ----------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -16,16 +16,19 @@
#define LLVM_CODEGEN_SCHEDULEDAGMUTATION_H
namespace llvm {
class ScheduleDAGInstrs;
/// Mutate the DAG as a postpass after normal DAG building.
class ScheduleDAGMutation {
virtual void anchor();
public:
virtual ~ScheduleDAGMutation() {}
class ScheduleDAGInstrs;
virtual void apply(ScheduleDAGInstrs *DAG) = 0;
};
}
/// Mutate the DAG as a postpass after normal DAG building.
class ScheduleDAGMutation {
virtual void anchor();
#endif
public:
virtual ~ScheduleDAGMutation() = default;
virtual void apply(ScheduleDAGInstrs *DAG) = 0;
};
} // end namespace llvm
#endif // LLVM_CODEGEN_SCHEDULEDAGMUTATION_H

26
include/llvm/CodeGen/ScheduleDFS.h
View File

@ -14,16 +14,16 @@
#ifndef LLVM_CODEGEN_SCHEDULEDFS_H
#define LLVM_CODEGEN_SCHEDULEDFS_H
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/Support/DataTypes.h"
#include <vector>
#include <cassert>
#include <cstdint>
namespace llvm {
class raw_ostream;
class IntEqClasses;
class ScheduleDAGInstrs;
class SUnit;
/// \brief Represent the ILP of the subDAG rooted at a DAG node.
///
@ -75,18 +75,18 @@ class SchedDFSResult {
/// interior node. Finally, it is set to a representative subtree ID during
/// finalization.
struct NodeData {
unsigned InstrCount;
unsigned SubtreeID;
unsigned InstrCount = 0;
unsigned SubtreeID = InvalidSubtreeID;
NodeData(): InstrCount(0), SubtreeID(InvalidSubtreeID) {}
NodeData() = default;
};
/// \brief Per-Subtree data computed during DFS.
struct TreeData {
unsigned ParentTreeID;
unsigned SubInstrCount;
unsigned ParentTreeID = InvalidSubtreeID;
unsigned SubInstrCount = 0;
TreeData(): ParentTreeID(InvalidSubtreeID), SubInstrCount(0) {}
TreeData() = default;
};
/// \brief Record a connection between subtrees and the connection level.
@ -107,7 +107,7 @@ class SchedDFSResult {
// For each subtree discovered during DFS, record its connections to other
// subtrees.
std::vector<SmallVector<Connection, 4> > SubtreeConnections;
std::vector<SmallVector<Connection, 4>> SubtreeConnections;
/// Cache the current connection level of each subtree.
/// This mutable array is updated during scheduling.
@ -189,6 +189,6 @@ public:
raw_ostream &operator<<(raw_ostream &OS, const ILPValue &Val);
} // namespace llvm
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_SCHEDULEDFS_H

8
include/llvm/CodeGen/ScheduleHazardRecognizer.h
View File

@ -29,10 +29,10 @@ protected:
/// state. Important to restore the state after backtracking. Additionally,
/// MaxLookAhead=0 identifies a fake recognizer, allowing the client to
/// bypass virtual calls. Currently the PostRA scheduler ignores it.
unsigned MaxLookAhead;
unsigned MaxLookAhead = 0;
public:
ScheduleHazardRecognizer(): MaxLookAhead(0) {}
ScheduleHazardRecognizer() = default;
virtual ~ScheduleHazardRecognizer();
enum HazardType {
@ -117,6 +117,6 @@ public:
}
};
}
} // end namespace llvm
#endif
#endif // LLVM_CODEGEN_SCHEDULEHAZARDRECOGNIZER_H

22
include/llvm/CodeGen/ScoreboardHazardRecognizer.h
View File

@ -17,8 +17,8 @@
#define LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/Support/DataTypes.h"
#include <cassert>
#include <cstddef>
#include <cstring>
namespace llvm {
@ -38,21 +38,25 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer {
// bottom-up scheduler, then the scoreboard cycles are the inverse of the
// scheduler's cycles.
class Scoreboard {
unsigned *Data;
unsigned *Data = nullptr;
// The maximum number of cycles monitored by the Scoreboard. This
// value is determined based on the target itineraries to ensure
// that all hazards can be tracked.
size_t Depth;
size_t Depth = 0;
// Indices into the Scoreboard that represent the current cycle.
size_t Head;
size_t Head = 0;
public:
Scoreboard():Data(nullptr), Depth(0), Head(0) { }
Scoreboard() = default;
~Scoreboard() {
delete[] Data;
}
size_t getDepth() const { return Depth; }
unsigned& operator[](size_t idx) const {
// Depth is expected to be a power-of-2.
assert(Depth && !(Depth & (Depth - 1)) &&
@ -93,10 +97,10 @@ class ScoreboardHazardRecognizer : public ScheduleHazardRecognizer {
const ScheduleDAG *DAG;
/// IssueWidth - Max issue per cycle. 0=Unknown.
unsigned IssueWidth;
unsigned IssueWidth = 0;
/// IssueCount - Count instructions issued in this cycle.
unsigned IssueCount;
unsigned IssueCount = 0;
Scoreboard ReservedScoreboard;
Scoreboard RequiredScoreboard;
@ -119,6 +123,6 @@ public:
void RecedeCycle() override;
};
}
} // end namespace llvm
#endif //!LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H
#endif // LLVM_CODEGEN_SCOREBOARDHAZARDRECOGNIZER_H

51
include/llvm/CodeGen/StackMaps.h
View File

@ -1,4 +1,4 @@
//===------------------- StackMaps.h - StackMaps ----------------*- C++ -*-===//
//===- StackMaps.h - StackMaps ----------------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -13,7 +13,11 @@
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/IR/CallingConv.h"
#include "llvm/Support/Debug.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <vector>
namespace llvm {
@ -21,6 +25,9 @@ namespace llvm {
class AsmPrinter;
class MCExpr;
class MCStreamer;
class MCSymbol;
class raw_ostream;
class TargetRegisterInfo;
/// \brief MI-level stackmap operands.
///
@ -189,21 +196,22 @@ public:
Constant,
ConstantIndex
};
LocationType Type;
unsigned Size;
unsigned Reg;
int64_t Offset;
Location() : Type(Unprocessed), Size(0), Reg(0), Offset(0) {}
LocationType Type = Unprocessed;
unsigned Size = 0;
unsigned Reg = 0;
int64_t Offset = 0;
Location() = default;
Location(LocationType Type, unsigned Size, unsigned Reg, int64_t Offset)
: Type(Type), Size(Size), Reg(Reg), Offset(Offset) {}
};
struct LiveOutReg {
unsigned short Reg;
unsigned short DwarfRegNum;
unsigned short Size;
unsigned short Reg = 0;
unsigned short DwarfRegNum = 0;
unsigned short Size = 0;
LiveOutReg() : Reg(0), DwarfRegNum(0), Size(0) {}
LiveOutReg() = default;
LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum,
unsigned short Size)
: Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {}
@ -245,18 +253,20 @@ private:
typedef MapVector<uint64_t, uint64_t> ConstantPool;
struct FunctionInfo {
uint64_t StackSize;
uint64_t RecordCount;
FunctionInfo() : StackSize(0), RecordCount(1) {}
explicit FunctionInfo(uint64_t StackSize) : StackSize(StackSize), RecordCount(1) {}
uint64_t StackSize = 0;
uint64_t RecordCount = 1;
FunctionInfo() = default;
explicit FunctionInfo(uint64_t StackSize) : StackSize(StackSize) {}
};
struct CallsiteInfo {
const MCExpr *CSOffsetExpr;
uint64_t ID;
const MCExpr *CSOffsetExpr = nullptr;
uint64_t ID = 0;
LocationVec Locations;
LiveOutVec LiveOuts;
CallsiteInfo() : CSOffsetExpr(nullptr), ID(0) {}
CallsiteInfo() = default;
CallsiteInfo(const MCExpr *CSOffsetExpr, uint64_t ID,
LocationVec &&Locations, LiveOutVec &&LiveOuts)
: CSOffsetExpr(CSOffsetExpr), ID(ID), Locations(std::move(Locations)),
@ -309,6 +319,7 @@ private:
void print(raw_ostream &OS);
void debug() { print(dbgs()); }
};
}
#endif
} // end namespace llvm
#endif // LLVM_CODEGEN_STACKMAPS_H

18
include/llvm/CodeGen/StackProtector.h
View File

@ -1,4 +1,4 @@
//===-- StackProtector.h - Stack Protector Insertion ----------------------===//
//===- StackProtector.h - Stack Protector Insertion -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -23,8 +23,10 @@
#include "llvm/IR/ValueMap.h"
#include "llvm/Pass.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {
class Function;
class Module;
class PHINode;
@ -48,11 +50,11 @@ public:
typedef ValueMap<const AllocaInst *, SSPLayoutKind> SSPLayoutMap;
private:
const TargetMachine *TM;
const TargetMachine *TM = nullptr;
/// TLI - Keep a pointer of a TargetLowering to consult for determining
/// target type sizes.
const TargetLoweringBase *TLI;
const TargetLoweringBase *TLI = nullptr;
const Triple Trip;
Function *F;
@ -67,7 +69,7 @@ private:
/// \brief The minimum size of buffers that will receive stack smashing
/// protection when -fstack-protection is used.
unsigned SSPBufferSize;
unsigned SSPBufferSize = 0;
/// VisitedPHIs - The set of PHI nodes visited when determining
/// if a variable's reference has been taken. This set
@ -111,12 +113,13 @@ private:
public:
static char ID; // Pass identification, replacement for typeid.
StackProtector()
: FunctionPass(ID), TM(nullptr), TLI(nullptr), SSPBufferSize(0) {
StackProtector() : FunctionPass(ID) {
initializeStackProtectorPass(*PassRegistry::getPassRegistry());
}
StackProtector(const TargetMachine *TM)
: FunctionPass(ID), TM(TM), TLI(nullptr), Trip(TM->getTargetTriple()),
: FunctionPass(ID), TM(TM), Trip(TM->getTargetTriple()),
SSPBufferSize(8) {
initializeStackProtectorPass(*PassRegistry::getPassRegistry());
}
@ -134,6 +137,7 @@ public:
bool runOnFunction(Function &Fn) override;
};
} // end namespace llvm
#endif // LLVM_CODEGEN_STACKPROTECTOR_H

137
lib/CodeGen/MachineScheduler.cpp
View File

@ -12,30 +12,67 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/iterator_range.h"
#include "llvm/ADT/PriorityQueue.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
#include "llvm/CodeGen/RegisterPressure.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/CodeGen/MachineValueType.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleDAGInstrs.h"
#include "llvm/CodeGen/ScheduleDAGMutation.h"
#include "llvm/CodeGen/ScheduleDFS.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/LaneBitmask.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/GraphWriter.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <limits>
#include <memory>
#include <string>
#include <tuple>
#include <utility>
#include <vector>
using namespace llvm;
#define DEBUG_TYPE "misched"
namespace llvm {
cl::opt<bool> ForceTopDown("misched-topdown", cl::Hidden,
cl::desc("Force top-down list scheduling"));
cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
@ -43,7 +80,8 @@ cl::opt<bool> ForceBottomUp("misched-bottomup", cl::Hidden,
cl::opt<bool>
DumpCriticalPathLength("misched-dcpl", cl::Hidden,
cl::desc("Print critical path length to stdout"));
}
} // end namespace llvm
#ifndef NDEBUG
static cl::opt<bool> ViewMISchedDAGs("view-misched-dags", cl::Hidden,
@ -88,14 +126,14 @@ static const unsigned MinSubtreeSize = 8;
// Pin the vtables to this file.
void MachineSchedStrategy::anchor() {}
void ScheduleDAGMutation::anchor() {}
//===----------------------------------------------------------------------===//
// Machine Instruction Scheduling Pass and Registry
//===----------------------------------------------------------------------===//
MachineSchedContext::MachineSchedContext():
MF(nullptr), MLI(nullptr), MDT(nullptr), PassConfig(nullptr), AA(nullptr), LIS(nullptr) {
MachineSchedContext::MachineSchedContext() {
RegClassInfo = new RegisterClassInfo();
}
@ -104,6 +142,7 @@ MachineSchedContext::~MachineSchedContext() {
}
namespace {
/// Base class for a machine scheduler class that can run at any point.
class MachineSchedulerBase : public MachineSchedContext,
public MachineFunctionPass {
@ -145,7 +184,8 @@ public:
protected:
ScheduleDAGInstrs *createPostMachineScheduler();
};
} // namespace
} // end anonymous namespace
char MachineScheduler::ID = 0;
@ -207,7 +247,7 @@ static ScheduleDAGInstrs *useDefaultMachineSched(MachineSchedContext *C) {
/// MachineSchedOpt allows command line selection of the scheduler.
static cl::opt<MachineSchedRegistry::ScheduleDAGCtor, false,
RegisterPassParser<MachineSchedRegistry> >
RegisterPassParser<MachineSchedRegistry>>
MachineSchedOpt("misched",
cl::init(&useDefaultMachineSched), cl::Hidden,
cl::desc("Machine instruction scheduler to use"));
@ -444,7 +484,7 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
// instruction stream until we find the nearest boundary.
unsigned NumRegionInstrs = 0;
MachineBasicBlock::iterator I = RegionEnd;
for (;I != MBB->begin(); --I) {
for (; I != MBB->begin(); --I) {
MachineInstr &MI = *std::prev(I);
if (isSchedBoundary(&MI, &*MBB, MF, TII))
break;
@ -516,8 +556,7 @@ LLVM_DUMP_METHOD void ReadyQueue::dump() {
// ===----------------------------------------------------------------------===/
// Provide a vtable anchor.
ScheduleDAGMI::~ScheduleDAGMI() {
}
ScheduleDAGMI::~ScheduleDAGMI() = default;
bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
return SuccSU == &ExitSU || !Topo.IsReachable(PredSU, SuccSU);
@ -822,7 +861,7 @@ void ScheduleDAGMI::placeDebugValues() {
RegionBegin = FirstDbgValue;
}
for (std::vector<std::pair<MachineInstr *, MachineInstr *> >::iterator
for (std::vector<std::pair<MachineInstr *, MachineInstr *>>::iterator
DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) {
std::pair<MachineInstr *, MachineInstr *> P = *std::prev(DI);
MachineInstr *DbgValue = P.first;
@ -1009,7 +1048,7 @@ updateScheduledPressure(const SUnit *SU,
++CritIdx;
if (CritIdx != CritEnd && RegionCriticalPSets[CritIdx].getPSet() == ID) {
if ((int)NewMaxPressure[ID] > RegionCriticalPSets[CritIdx].getUnitInc()
&& NewMaxPressure[ID] <= INT16_MAX)
&& NewMaxPressure[ID] <= std::numeric_limits<int16_t>::max())
RegionCriticalPSets[CritIdx].setUnitInc(NewMaxPressure[ID]);
}
unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
@ -1393,6 +1432,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
//===----------------------------------------------------------------------===//
namespace {
/// \brief Post-process the DAG to create cluster edges between neighboring
/// loads or between neighboring stores.
class BaseMemOpClusterMutation : public ScheduleDAGMutation {
@ -1400,6 +1440,7 @@ class BaseMemOpClusterMutation : public ScheduleDAGMutation {
SUnit *SU;
unsigned BaseReg;
int64_t Offset;
MemOpInfo(SUnit *su, unsigned reg, int64_t ofs)
: SU(su), BaseReg(reg), Offset(ofs) {}
@ -1436,25 +1477,26 @@ public:
LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
: BaseMemOpClusterMutation(tii, tri, true) {}
};
} // anonymous
} // end anonymous namespace
namespace llvm {
std::unique_ptr<ScheduleDAGMutation>
createLoadClusterDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
return EnableMemOpCluster ? make_unique<LoadClusterMutation>(TII, TRI)
return EnableMemOpCluster ? llvm::make_unique<LoadClusterMutation>(TII, TRI)
: nullptr;
}
std::unique_ptr<ScheduleDAGMutation>
createStoreClusterDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
return EnableMemOpCluster ? make_unique<StoreClusterMutation>(TII, TRI)
return EnableMemOpCluster ? llvm::make_unique<StoreClusterMutation>(TII, TRI)
: nullptr;
}
} // namespace llvm
} // end namespace llvm
void BaseMemOpClusterMutation::clusterNeighboringMemOps(
ArrayRef<SUnit *> MemOps, ScheduleDAGMI *DAG) {
@ -1544,6 +1586,7 @@ void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
//===----------------------------------------------------------------------===//
namespace {
/// \brief Post-process the DAG to create weak edges from all uses of a copy to
/// the one use that defines the copy's source vreg, most likely an induction
/// variable increment.
@ -1553,6 +1596,7 @@ class CopyConstrain : public ScheduleDAGMutation {
// RegionEndIdx is the slot index of the last non-debug instruction in the
// scheduling region. So we may have RegionBeginIdx == RegionEndIdx.
SlotIndex RegionEndIdx;
public:
CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
@ -1561,17 +1605,18 @@ public:
protected:
void constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG);
};
} // anonymous
} // end anonymous namespace
namespace llvm {
std::unique_ptr<ScheduleDAGMutation>
createCopyConstrainDAGMutation(const TargetInstrInfo *TII,
const TargetRegisterInfo *TRI) {
return make_unique<CopyConstrain>(TII, TRI);
const TargetRegisterInfo *TRI) {
return llvm::make_unique<CopyConstrain>(TII, TRI);
}
} // namespace llvm
} // end namespace llvm
/// constrainLocalCopy handles two possibilities:
/// 1) Local src:
@ -1763,7 +1808,7 @@ void SchedBoundary::reset() {
CheckPending = false;
CurrCycle = 0;
CurrMOps = 0;
MinReadyCycle = UINT_MAX;
MinReadyCycle = std::numeric_limits<unsigned>::max();
ExpectedLatency = 0;
DependentLatency = 0;
RetiredMOps = 0;
@ -1966,7 +2011,8 @@ void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle) {
/// Move the boundary of scheduled code by one cycle.
void SchedBoundary::bumpCycle(unsigned NextCycle) {
if (SchedModel->getMicroOpBufferSize() == 0) {
assert(MinReadyCycle < UINT_MAX && "MinReadyCycle uninitialized");
assert(MinReadyCycle < std::numeric_limits<unsigned>::max() &&
"MinReadyCycle uninitialized");
if (MinReadyCycle > NextCycle)
NextCycle = MinReadyCycle;
}
@ -2177,7 +2223,7 @@ void SchedBoundary::bumpNode(SUnit *SU) {
void SchedBoundary::releasePending() {
// If the available queue is empty, it is safe to reset MinReadyCycle.
if (Available.empty())
MinReadyCycle = UINT_MAX;
MinReadyCycle = std::numeric_limits<unsigned>::max();
// Check to see if any of the pending instructions are ready to issue. If
// so, add them to the available queue.
@ -3036,7 +3082,6 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
}
void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
MachineBasicBlock::iterator InsertPos = SU->getInstr();
if (!isTop)
++InsertPos;
@ -3084,7 +3129,8 @@ void GenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
/// Create the standard converging machine scheduler. This will be used as the
/// default scheduler if the target does not set a default.
ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) {
ScheduleDAGMILive *DAG = new ScheduleDAGMILive(C, make_unique<GenericScheduler>(C));
ScheduleDAGMILive *DAG =
new ScheduleDAGMILive(C, llvm::make_unique<GenericScheduler>(C));
// Register DAG post-processors.
//
// FIXME: extend the mutation API to allow earlier mutations to instantiate
@ -3125,7 +3171,6 @@ void PostGenericScheduler::initialize(ScheduleDAGMI *Dag) {
}
}
void PostGenericScheduler::registerRoots() {
Rem.CriticalPath = DAG->ExitSU.getDepth();
@ -3232,7 +3277,7 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) {
}
ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
return new ScheduleDAGMI(C, make_unique<PostGenericScheduler>(C),
return new ScheduleDAGMI(C, llvm::make_unique<PostGenericScheduler>(C),
/*RemoveKillFlags=*/true);
}
@ -3241,14 +3286,14 @@ ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) {
//===----------------------------------------------------------------------===//
namespace {
/// \brief Order nodes by the ILP metric.
struct ILPOrder {
const SchedDFSResult *DFSResult;
const BitVector *ScheduledTrees;
const SchedDFSResult *DFSResult = nullptr;
const BitVector *ScheduledTrees = nullptr;
bool MaximizeILP;
ILPOrder(bool MaxILP)
: DFSResult(nullptr), ScheduledTrees(nullptr), MaximizeILP(MaxILP) {}
ILPOrder(bool MaxILP) : MaximizeILP(MaxILP) {}
/// \brief Apply a less-than relation on node priority.
///
@ -3277,12 +3322,13 @@ struct ILPOrder {
/// \brief Schedule based on the ILP metric.
class ILPScheduler : public MachineSchedStrategy {
ScheduleDAGMILive *DAG;
ScheduleDAGMILive *DAG = nullptr;
ILPOrder Cmp;
std::vector<SUnit*> ReadyQ;
public:
ILPScheduler(bool MaximizeILP): DAG(nullptr), Cmp(MaximizeILP) {}
ILPScheduler(bool MaximizeILP) : Cmp(MaximizeILP) {}
void initialize(ScheduleDAGMI *dag) override {
assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness");
@ -3335,14 +3381,16 @@ public:
std::push_heap(ReadyQ.begin(), ReadyQ.end(), Cmp);
}
};
} // namespace
} // end anonymous namespace
static ScheduleDAGInstrs *createILPMaxScheduler(MachineSchedContext *C) {
return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(true));
return new ScheduleDAGMILive(C, llvm::make_unique<ILPScheduler>(true));
}
static ScheduleDAGInstrs *createILPMinScheduler(MachineSchedContext *C) {
return new ScheduleDAGMILive(C, make_unique<ILPScheduler>(false));
return new ScheduleDAGMILive(C, llvm::make_unique<ILPScheduler>(false));
}
static MachineSchedRegistry ILPMaxRegistry(
"ilpmax", "Schedule bottom-up for max ILP", createILPMaxScheduler);
static MachineSchedRegistry ILPMinRegistry(
@ -3354,6 +3402,7 @@ static MachineSchedRegistry ILPMinRegistry(
#ifndef NDEBUG
namespace {
/// Apply a less-than relation on the node order, which corresponds to the
/// instruction order prior to scheduling. IsReverse implements greater-than.
template<bool IsReverse>
@ -3374,11 +3423,12 @@ class InstructionShuffler : public MachineSchedStrategy {
// Using a less-than relation (SUnitOrder<false>) for the TopQ priority
// gives nodes with a higher number higher priority causing the latest
// instructions to be scheduled first.
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false> >
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<false>>
TopQ;
// When scheduling bottom-up, use greater-than as the queue priority.
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true> >
PriorityQueue<SUnit*, std::vector<SUnit*>, SUnitOrder<true>>
BottomQ;
public:
InstructionShuffler(bool alternate, bool topdown)
: IsAlternating(alternate), IsTopDown(topdown) {}
@ -3422,15 +3472,18 @@ public:
BottomQ.push(SU);
}
};
} // namespace
} // end anonymous namespace
static ScheduleDAGInstrs *createInstructionShuffler(MachineSchedContext *C) {
bool Alternate = !ForceTopDown && !ForceBottomUp;
bool TopDown = !ForceBottomUp;
assert((TopDown || !ForceTopDown) &&
"-misched-topdown incompatible with -misched-bottomup");
return new ScheduleDAGMILive(C, make_unique<InstructionShuffler>(Alternate, TopDown));
return new ScheduleDAGMILive(
C, llvm::make_unique<InstructionShuffler>(Alternate, TopDown));
}
static MachineSchedRegistry ShufflerRegistry(
"shuffle", "Shuffle machine instructions alternating directions",
createInstructionShuffler);
@ -3448,8 +3501,7 @@ template<> struct GraphTraits<
template<>
struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
DOTGraphTraits (bool isSimple=false) : DefaultDOTGraphTraits(isSimple) {}
DOTGraphTraits(bool isSimple = false) : DefaultDOTGraphTraits(isSimple) {}
static std::string getGraphName(const ScheduleDAG *G) {
return G->MF.getName();
@ -3506,7 +3558,8 @@ struct DOTGraphTraits<ScheduleDAGMI*> : public DefaultDOTGraphTraits {
return Str;
}
};
} // namespace llvm
} // end namespace llvm
#endif // NDEBUG
/// viewGraph - Pop up a ghostview window with the reachable parts of the DAG

43
lib/CodeGen/ScheduleDAG.cpp
View File

@ -1,4 +1,4 @@
//===---- ScheduleDAG.cpp - Implement the ScheduleDAG class ---------------===//
//===- ScheduleDAG.cpp - Implement the ScheduleDAG class ------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -12,17 +12,27 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/ADT/iterator_range.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <climits>
#include <algorithm>
#include <cassert>
#include <iterator>
#include <limits>
#include <utility>
#include <vector>
using namespace llvm;
#define DEBUG_TYPE "pre-RA-sched"
@ -33,18 +43,18 @@ static cl::opt<bool> StressSchedOpt(
cl::desc("Stress test instruction scheduling"));
#endif
void SchedulingPriorityQueue::anchor() { }
void SchedulingPriorityQueue::anchor() {}
ScheduleDAG::ScheduleDAG(MachineFunction &mf)
: TM(mf.getTarget()), TII(mf.getSubtarget().getInstrInfo()),
TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
MRI(mf.getRegInfo()), EntrySU(), ExitSU() {
MRI(mf.getRegInfo()) {
#ifndef NDEBUG
StressSched = StressSchedOpt;
#endif
}
ScheduleDAG::~ScheduleDAG() {}
ScheduleDAG::~ScheduleDAG() = default;
void ScheduleDAG::clearDAG() {
SUnits.clear();
@ -89,8 +99,10 @@ bool SUnit::addPred(const SDep &D, bool Required) {
SUnit *N = D.getSUnit();
// Update the bookkeeping.
if (D.getKind() == SDep::Data) {
assert(NumPreds < UINT_MAX && "NumPreds will overflow!");
assert(N->NumSuccs < UINT_MAX && "NumSuccs will overflow!");
assert(NumPreds < std::numeric_limits<unsigned>::max() &&
"NumPreds will overflow!");
assert(N->NumSuccs < std::numeric_limits<unsigned>::max() &&
"NumSuccs will overflow!");
++NumPreds;
++N->NumSuccs;
}
@ -99,7 +111,8 @@ bool SUnit::addPred(const SDep &D, bool Required) {
++WeakPredsLeft;
}
else {
assert(NumPredsLeft < UINT_MAX && "NumPredsLeft will overflow!");
assert(NumPredsLeft < std::numeric_limits<unsigned>::max() &&
"NumPredsLeft will overflow!");
++NumPredsLeft;
}
}
@ -108,7 +121,8 @@ bool SUnit::addPred(const SDep &D, bool Required) {
++N->WeakSuccsLeft;
}
else {
assert(N->NumSuccsLeft < UINT_MAX && "NumSuccsLeft will overflow!");
assert(N->NumSuccsLeft < std::numeric_limits<unsigned>::max() &&
"NumSuccsLeft will overflow!");
++N->NumSuccsLeft;
}
}
@ -123,14 +137,14 @@ bool SUnit::addPred(const SDep &D, bool Required) {
void SUnit::removePred(const SDep &D) {
// Find the matching predecessor.
SmallVectorImpl<SDep>::iterator I = find(Preds, D);
SmallVectorImpl<SDep>::iterator I = llvm::find(Preds, D);
if (I == Preds.end())
return;
// Find the corresponding successor in N.
SDep P = D;
P.setSUnit(this);
SUnit *N = D.getSUnit();
SmallVectorImpl<SDep>::iterator Succ = find(N->Succs, P);
SmallVectorImpl<SDep>::iterator Succ = llvm::find(N->Succs, P);
assert(Succ != N->Succs.end() && "Mismatching preds / succs lists!");
N->Succs.erase(Succ);
Preds.erase(I);
@ -376,7 +390,7 @@ unsigned ScheduleDAG::VerifyScheduledDAG(bool isBottomUp) {
}
if (SUnit.isScheduled &&
(isBottomUp ? SUnit.getHeight() : SUnit.getDepth()) >
unsigned(INT_MAX)) {
unsigned(std::numeric_limits<int>::max())) {
if (!AnyNotSched)
dbgs() << "*** Scheduling failed! ***\n";
SUnit.dump(this);
@ -559,7 +573,6 @@ void ScheduleDAGTopologicalSort::Shift(BitVector& Visited, int LowerBound,
}
}
bool ScheduleDAGTopologicalSort::WillCreateCycle(SUnit *TargetSU, SUnit *SU) {
// Is SU reachable from TargetSU via successor edges?
if (IsReachable(SU, TargetSU))
@ -597,4 +610,4 @@ ScheduleDAGTopologicalSort::
ScheduleDAGTopologicalSort(std::vector<SUnit> &sunits, SUnit *exitsu)
: SUnits(sunits), ExitSU(exitsu) {}
ScheduleHazardRecognizer::~ScheduleHazardRecognizer() {}
ScheduleHazardRecognizer::~ScheduleHazardRecognizer() = default;

9
lib/CodeGen/ScoreboardHazardRecognizer.cpp
View File

@ -1,4 +1,4 @@
//===----- ScoreboardHazardRecognizer.cpp - Scheduler Support -------------===//
//===- ScoreboardHazardRecognizer.cpp - Scheduler Support -----------------===//
//
// The LLVM Compiler Infrastructure
//
@ -15,11 +15,13 @@
#include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
#include "llvm/CodeGen/ScheduleDAG.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include <cassert>
using namespace llvm;
@ -29,8 +31,7 @@ ScoreboardHazardRecognizer::ScoreboardHazardRecognizer(
const InstrItineraryData *II, const ScheduleDAG *SchedDAG,
const char *ParentDebugType)
: ScheduleHazardRecognizer(), DebugType(ParentDebugType), ItinData(II),
DAG(SchedDAG), IssueWidth(0), IssueCount(0) {
DAG(SchedDAG) {
// Determine the maximum depth of any itinerary. This determines the depth of
// the scoreboard. We always make the scoreboard at least 1 cycle deep to
// avoid dealing with the boundary condition.

24
lib/CodeGen/StackMaps.cpp
View File

@ -1,4 +1,4 @@
//===---------------------------- StackMaps.cpp ---------------------------===//
//===- StackMaps.cpp ------------------------------------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,23 +7,34 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/ADT/DenseMapInfo.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Twine.h"
#include "llvm/CodeGen/AsmPrinter.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCSectionMachO.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetOpcodes.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
#include <cassert>
#include <cstdint>
#include <iterator>
#include <utility>
using namespace llvm;
@ -276,7 +287,8 @@ StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
}
LiveOuts.erase(
remove_if(LiveOuts, [](const LiveOutReg &LO) { return LO.Reg == 0; }),
llvm::remove_if(LiveOuts,
[](const LiveOutReg &LO) { return LO.Reg == 0; }),
LiveOuts.end());
return LiveOuts;
@ -286,7 +298,6 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
MachineInstr::const_mop_iterator MOI,
MachineInstr::const_mop_iterator MOE,
bool recordResult) {
MCContext &OutContext = AP.OutStreamer->getContext();
MCSymbol *MILabel = OutContext.createTempSymbol();
AP.OutStreamer->EmitLabel(MILabel);
@ -378,6 +389,7 @@ void StackMaps::recordPatchPoint(const MachineInstr &MI) {
}
#endif
}
void StackMaps::recordStatepoint(const MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::STATEPOINT && "expected statepoint");

21
lib/CodeGen/StackProtector.cpp
View File

@ -1,4 +1,4 @@
//===-- StackProtector.cpp - Stack Protector Insertion --------------------===//
//===- StackProtector.cpp - Stack Protector Insertion ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -14,30 +14,37 @@
//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/Analysis/BranchProbabilityInfo.h"
#include "llvm/Analysis/EHPersonalities.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/Passes.h"
#include "llvm/CodeGen/StackProtector.h"
#include "llvm/IR/Attributes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/DebugInfo.h"
#include "llvm/IR/DebugLoc.h"
#include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/IR/GlobalVariable.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instruction.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicInst.h"
#include "llvm/IR/Intrinsics.h"
#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/Module.h"
#include "llvm/IR/Type.h"
#include "llvm/IR/User.h"
#include "llvm/Pass.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <cstdlib>
#include <utility>
using namespace llvm;
#define DEBUG_TYPE "stack-protector"