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[VPlan] Move test strs to variables, silence spurious C4129 (NFC).
This is a speculative fix to silence the spurious C4129 warning that some version of MSVC generate for the raw string literals in the changed files. Before disabling the warning (D76428), try a potential fix suggested in the review.
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@ -94,7 +94,7 @@ TEST_F(VPlanHCFGTest, testBuildHCFGInnerLoop) {
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Plan->addVPValue(&*F->arg_begin());
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std::string FullDump;
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raw_string_ostream(FullDump) << *Plan;
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EXPECT_EQ(R"(digraph VPlan {
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const char *ExpectedStr = R"(digraph VPlan {
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graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
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node [shape=rect, fontname=Courier, fontsize=30]
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edge [fontname=Courier, fontsize=30]
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@ -125,8 +125,8 @@ compound=true
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]
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}
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}
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)",
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FullDump);
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)";
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EXPECT_EQ(ExpectedStr, FullDump);
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LoopVectorizationLegality::InductionList Inductions;
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SmallPtrSet<Instruction *, 1> DeadInstructions;
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@ -209,7 +209,7 @@ TEST(VPBasicBlockTest, print) {
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std::string FullDump;
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raw_string_ostream(FullDump) << Plan;
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EXPECT_EQ(R"(digraph VPlan {
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const char *ExpectedStr = R"(digraph VPlan {
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graph [labelloc=t, fontsize=30; label="Vectorization Plan"]
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node [shape=rect, fontname=Courier, fontsize=30]
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edge [fontname=Courier, fontsize=30]
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@ -227,8 +227,8 @@ compound=true
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"EMIT ret vp<%2>\l"
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]
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}
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)",
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FullDump);
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)";
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EXPECT_EQ(ExpectedStr, FullDump);
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{
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std::string I3Dump;
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