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[Thumb] 32-bit encodings of 'cps' are not valid for v7M

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v7M only allows the 16-bit encoding of the 'cps' (Change Processor
State) instruction, and does not have the 32-bit encoding which is
valid from v6T2 onwards.

llvm-svn: 218382
This commit is contained in:
Oliver Stannard 2014-09-24 14:20:01 +00:00
parent 58b3f6f4cc
commit 8ccbd5af71
3 changed files with 21 additions and 1 deletions
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3
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3674,7 +3674,8 @@ let isBranch = 1, isTerminator = 1 in {
// operands, create 3 versions of the same instruction. Once there's a clean
// framework to represent optional operands, change this behavior.
class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary,
!strconcat("cps", asm_op), []> {
!strconcat("cps", asm_op), []>,
Requires<[IsThumb2, IsNotMClass]> {
bits<2> imod;
bits<3> iflags;
bits<5> mode;

2
lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@ -5514,6 +5514,8 @@ bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
Operands.push_back(ARMOperand::CreateImm(
MCConstantExpr::Create(ProcessorIMod, getContext()),
NameLoc, NameLoc));
} else if (Mnemonic == "cps" && isMClass()) {
return Error(NameLoc, "instruction 'cps' requires effect for M-class");
}
// Add the remaining tokens in the mnemonic.

17
test/MC/ARM/cps.s Normal file
View File

@ -0,0 +1,17 @@
@ RUN: llvm-mc -triple=thumbv6t2--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple=thumbv7a--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple=thumbv7r--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: llvm-mc -triple=thumbv8a--none-eabi -show-encoding < %s | FileCheck %s
@ RUN: not llvm-mc -triple=thumbv7m--none-eabi -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=UNDEF
cpsie f
cpsie i, #3
cps #0
@ CHECK: cpsie f @ encoding: [0x61,0xb6]
@ CHECK: cpsie i, #3 @ encoding: [0xaf,0xf3,0x43,0x85]
@ CHECK: cps #0 @ encoding: [0xaf,0xf3,0x00,0x81]
@ UNDEF-DAG: cpsie f @ encoding: [0x61,0xb6]
@ UNDEF-DAG: error: instruction requires:
@ UNDEF-DAG: error: instruction 'cps' requires effect for M-class