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When optimizing certain BUILD_VECTOR nodes into other BUILD_VECTOR nodes, add the new node into the work list because there is a potential for further optimizations.

llvm-svn: 152784
This commit is contained in:
Nadav Rotem 2012-03-15 08:49:06 +00:00
parent 0711b41ec6
commit 8cf9105f96
2 changed files with 14 additions and 0 deletions

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@ -7422,6 +7422,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
// will be type-legalized to complex code sequences.
// We perform this optimization only before the operation legalizer because we
// may introduce illegal operations.
// Create a new simpler BUILD_VECTOR sequence which other optimizations can
// turn into a single shuffle instruction.
if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) &&
ValidTypes) {
bool isLE = TLI.isLittleEndian();
@ -7462,6 +7464,8 @@ SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
VecVT, &Ops[0], Ops.size());
// The new BUILD_VECTOR node has the potential to be further optimized.
AddToWorkList(BV.getNode());
// Bitcast to the desired type.
return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV);
}

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@ -0,0 +1,10 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
; CHECK: build_vector_again
define <4 x i8> @build_vector_again(<16 x i8> %in) nounwind readnone {
entry:
%out = shufflevector <16 x i8> %in, <16 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK: shufb
ret <4 x i8> %out
; CHECK: ret
}