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[AMDGPU] support image load/store a16
Our a16 support was only enabled for sample/gather and buffer load/store, but not for image load/store operations (which take an i16 as the pixel index rather than a half). Fix our isel lowering and add test cases to prove it out. Differential Revision: https://reviews.llvm.org/D53750 llvm-svn: 345710
This commit is contained in:
Neil Henning
parent
a704bd2a52
commit
8d00d20845
@ -4726,9 +4726,11 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
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// Check for 16 bit addresses and pack if true.
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unsigned DimIdx = AddrIdx + BaseOpcode->NumExtraArgs;
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MVT VAddrVT = Op.getOperand(DimIdx).getSimpleValueType();
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if (VAddrVT.getScalarType() == MVT::f16 &&
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const MVT VAddrScalarVT = VAddrVT.getScalarType();
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if (((VAddrScalarVT == MVT::f16) || (VAddrScalarVT == MVT::i16)) &&
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ST->hasFeature(AMDGPU::FeatureR128A16)) {
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IsA16 = true;
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const MVT VectorVT = VAddrScalarVT == MVT::f16 ? MVT::v2f16 : MVT::v2i16;
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for (unsigned i = AddrIdx; i < (AddrIdx + NumMIVAddrs); ++i) {
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SDValue AddrLo, AddrHi;
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// Push back extra arguments.
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@ -4747,7 +4749,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
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AddrHi = Op.getOperand(i + 1);
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i++;
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}
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AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v2f16,
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AddrLo = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VectorVT,
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{AddrLo, AddrHi});
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AddrLo = DAG.getBitcast(MVT::i32, AddrLo);
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}
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530
test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
Normal file
530
test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
Normal file
@ -0,0 +1,530 @@
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; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; GCN-LABEL: {{^}}load_1d:
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; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_2d:
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; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%t = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_3d:
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; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%r = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_cube:
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; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_1darray:
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; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%slice = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_2darray:
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; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_2dmsaa:
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; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%fragid = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_2darraymsaa:
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; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%fragid = extractelement <2 x i16> %coords_hi, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_mip_1d:
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; GCN: image_load_mip v[0:3], v0, s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%mip = extractelement <2 x i16> %coords, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_mip_2d:
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; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%mip = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_mip_3d:
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; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
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define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%r = extractelement <2 x i16> %coords_hi, i32 0
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%mip = extractelement <2 x i16> %coords_hi, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_mip_cube:
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; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%mip = extractelement <2 x i16> %coords_hi, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_mip_1darray:
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; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%slice = extractelement <2 x i16> %coords_lo, i32 1
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%mip = extractelement <2 x i16> %coords_hi, i32 0
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}load_mip_2darray:
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; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%mip = extractelement <2 x i16> %coords_hi, i32 1
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%v = call <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
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ret <4 x float> %v
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}
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; GCN-LABEL: {{^}}store_1d:
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; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16
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define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_2d:
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; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16
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define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%t = extractelement <2 x i16> %coords, i32 1
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call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_3d:
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; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
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define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%r = extractelement <2 x i16> %coords_hi, i32 0
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call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_cube:
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; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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call void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_1darray:
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; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
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main_body:
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%s = extractelement <2 x i16> %coords, i32 0
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%slice = extractelement <2 x i16> %coords, i32 1
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call void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_2darray:
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; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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call void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_2dmsaa:
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; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
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define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%fragid = extractelement <2 x i16> %coords_hi, i32 0
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call void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
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ret void
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}
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; GCN-LABEL: {{^}}store_2darraymsaa:
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; GCN: image_store v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
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define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
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main_body:
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%s = extractelement <2 x i16> %coords_lo, i32 0
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%t = extractelement <2 x i16> %coords_lo, i32 1
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%slice = extractelement <2 x i16> %coords_hi, i32 0
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%fragid = extractelement <2 x i16> %coords_hi, i32 1
|
||||
call void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_1d:
|
||||
; GCN: image_store_mip v[0:3], v4, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
%mip = extractelement <2 x i16> %coords, i32 1
|
||||
call void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_2d:
|
||||
; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%mip = extractelement <2 x i16> %coords_hi, i32 0
|
||||
call void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_3d:
|
||||
; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%r = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||||
call void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %r, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_cube:
|
||||
; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||||
call void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_1darray:
|
||||
; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%slice = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%mip = extractelement <2 x i16> %coords_hi, i32 0
|
||||
call void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_mip_2darray:
|
||||
; GCN: image_store_mip v[0:3], v[4:5], s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%t = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%slice = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%mip = extractelement <2 x i16> %coords_hi, i32 1
|
||||
call void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, i16 %t, i16 %slice, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_1d:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2d:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_3d:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_cube:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_1darray:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2darray:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2dmsaa:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_2darraymsaa:
|
||||
; GCN: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf unorm a16 da{{$}}
|
||||
define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32 15, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_V1:
|
||||
; GCN: image_load v0, v0, s[0:7] dmask:0x8 unorm a16
|
||||
define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call float @llvm.amdgcn.image.load.1d.f32.i16(i32 8, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret float %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_V2:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x9 unorm a16
|
||||
define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32 9, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <2 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_V1:
|
||||
; GCN: image_store v0, v1, s[0:7] dmask:0x2 unorm a16
|
||||
define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.f32.i16(float %vdata, i32 2, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_V2:
|
||||
; GCN: image_store v[0:1], v2, s[0:7] dmask:0xc unorm a16
|
||||
define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float> %vdata, i32 12, i16 %s, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_glc:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc a16{{$}}
|
||||
define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_slc:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm slc a16{{$}}
|
||||
define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_1d_glc_slc:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm glc slc a16{{$}}
|
||||
define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_glc:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc a16{{$}}
|
||||
define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 1)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_slc:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm slc a16{{$}}
|
||||
define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 2)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store_1d_glc_slc:
|
||||
; GCN: image_store v[0:3], v4, s[0:7] dmask:0xf unorm glc slc a16{{$}}
|
||||
define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%s = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %vdata, i32 15, i16 %s, <8 x i32> %rsrc, i32 0, i32 3)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}getresinfo_dmask0:
|
||||
; GCN-NOT: image
|
||||
; GCN: ; return to shader part epilog
|
||||
define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x i16> %coords) #0 {
|
||||
main_body:
|
||||
%mip = extractelement <2 x i16> %coords, i32 0
|
||||
%r = call <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32 0, i16 %mip, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %r
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.cube.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.1darray.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.2darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.2dmsaa.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.1d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.2d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.3d.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.cube.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.1darray.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <4 x float> @llvm.amdgcn.image.load.mip.2darray.v4f32.i16(i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #1
|
||||
|
||||
declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.1darray.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.2dmsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.2darraymsaa.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
|
||||
declare void @llvm.amdgcn.image.store.mip.1d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.2d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.cube.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.1darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.mip.2darray.v4f32.i16(<4 x float>, i32, i16, i16, i16, i16, <8 x i32>, i32, i32) #0
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.2d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.3d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.cube.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.1darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.2darray.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.2dmsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.getresinfo.2darraymsaa.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
|
||||
declare float @llvm.amdgcn.image.load.1d.f32.i16(i32, i16, <8 x i32>, i32, i32) #1
|
||||
declare float @llvm.amdgcn.image.load.2d.f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #1
|
||||
declare <2 x float> @llvm.amdgcn.image.load.1d.v2f32.i16(i32, i16, <8 x i32>, i32, i32) #1
|
||||
declare void @llvm.amdgcn.image.store.1d.f32.i16(float, i32, i16, <8 x i32>, i32, i32) #0
|
||||
declare void @llvm.amdgcn.image.store.1d.v2f32.i16(<2 x float>, i32, i16, <8 x i32>, i32, i32) #0
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
attributes #2 = { nounwind readnone }
|
||||
128
test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
Normal file
128
test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.d16.ll
Normal file
@ -0,0 +1,128 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}load.f16.1d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v2f16.1d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v2f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v3f16.1d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v3f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v4f16.1d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.f16.2d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x1 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v2f16.2d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x3 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v2f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v3f16.2d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0x7 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v3f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v4f16.2d:
|
||||
; GCN: image_load v[0:1], v0, s[0:7] dmask:0xf unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v4f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.f16.3d:
|
||||
; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x1 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v2f16.3d:
|
||||
; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x3 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v2f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v3f16.3d:
|
||||
; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0x7 unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v3f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v4f16.3d:
|
||||
; GCN: image_load v[0:1], v[0:1], s[0:7] dmask:0xf unorm a16 d16
|
||||
define amdgpu_ps <4 x half> @load.v4f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x half> %v
|
||||
}
|
||||
|
||||
declare <4 x half> @llvm.amdgcn.image.load.1d.v4f16.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x half> @llvm.amdgcn.image.load.2d.v4f16.i16(i32, i16, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x half> @llvm.amdgcn.image.load.3d.v4f16.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
128
test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
Normal file
128
test/CodeGen/AMDGPU/llvm.amdgcn.image.load.a16.ll
Normal file
@ -0,0 +1,128 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}load.f32.1d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0x1 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v2f32.1d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0x3 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v3f32.1d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0x7 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v4f32.1d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.f32.2d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0x1 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v2f32.2d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0x3 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v3f32.2d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0x7 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v4f32.2d:
|
||||
; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.f32.3d:
|
||||
; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x1 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v2f32.3d:
|
||||
; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x3 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v3f32.3d:
|
||||
; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0x7 unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load.v4f32.3d:
|
||||
; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps <4 x float> @load.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%v = call <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret <4 x float> %v
|
||||
}
|
||||
|
||||
declare <4 x float> @llvm.amdgcn.image.load.1d.v4f32.i16(i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i16(i32, i16, i16, <8 x i32>, i32, i32) #2
|
||||
declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i16(i32, i16, i16, i16, <8 x i32>, i32, i32) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
140
test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
Normal file
140
test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.d16.ll
Normal file
@ -0,0 +1,140 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}store.f16.1d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16
|
||||
define amdgpu_ps void @store.f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v2f16.1d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16
|
||||
define amdgpu_ps void @store.v2f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v3f16.1d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16
|
||||
define amdgpu_ps void @store.v3f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v4f16.1d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16
|
||||
define amdgpu_ps void @store.v4f16.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.f16.2d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0x1 unorm a16 d16
|
||||
define amdgpu_ps void @store.f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v2f16.2d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0x3 unorm a16 d16
|
||||
define amdgpu_ps void @store.v2f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v3f16.2d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0x7 unorm a16 d16
|
||||
define amdgpu_ps void @store.v3f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v4f16.2d:
|
||||
; GCN: image_store v[1:2], v0, s[0:7] dmask:0xf unorm a16 d16
|
||||
define amdgpu_ps void @store.v4f16.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.f16.3d:
|
||||
; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x1 unorm a16 d16
|
||||
define amdgpu_ps void @store.f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v2f16.3d:
|
||||
; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 unorm a16 d16
|
||||
define amdgpu_ps void @store.v2f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v3f16.3d:
|
||||
; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0x7 unorm a16 d16
|
||||
define amdgpu_ps void @store.v3f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v4f16.3d:
|
||||
; GCN: image_store v[2:3], v[0:1], s[0:7] dmask:0xf unorm a16 d16
|
||||
define amdgpu_ps void @store.v4f16.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <2 x i32> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
%bitcast = bitcast <2 x i32> %val to <4 x half>
|
||||
call void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half> %bitcast, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.image.store.1d.v4f16.i16(<4 x half>, i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare void @llvm.amdgcn.image.store.2d.v4f16.i16(<4 x half>, i32, i16, i16, <8 x i32>, i32, i32) #2
|
||||
declare void @llvm.amdgcn.image.store.3d.v4f16.i16(<4 x half>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
128
test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
Normal file
128
test/CodeGen/AMDGPU/llvm.amdgcn.image.store.a16.ll
Normal file
@ -0,0 +1,128 @@
|
||||
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}store.f32.1d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16
|
||||
define amdgpu_ps void @store.f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v2f32.1d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0x3 unorm a16
|
||||
define amdgpu_ps void @store.v2f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v3f32.1d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0x7 unorm a16
|
||||
define amdgpu_ps void @store.v3f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v4f32.1d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps void @store.v4f32.1d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
call void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.f32.2d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0x1 unorm a16
|
||||
define amdgpu_ps void @store.f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v2f32.2d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0x3 unorm a16
|
||||
define amdgpu_ps void @store.v2f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v3f32.2d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0x7 unorm a16
|
||||
define amdgpu_ps void @store.v3f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v4f32.2d:
|
||||
; GCN: image_store v[1:4], v0, s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps void @store.v4f32.2d(<8 x i32> inreg %rsrc, <2 x i16> %coords, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords, i32 0
|
||||
%y = extractelement <2 x i16> %coords, i32 1
|
||||
call void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, i16 %y, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.f32.3d:
|
||||
; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x1 unorm a16
|
||||
define amdgpu_ps void @store.f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 1, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v2f32.3d:
|
||||
; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x3 unorm a16
|
||||
define amdgpu_ps void @store.v2f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 3, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v3f32.3d:
|
||||
; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0x7 unorm a16
|
||||
define amdgpu_ps void @store.v3f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 7, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}store.v4f32.3d:
|
||||
; GCN: image_store v[2:5], v[0:1], s[0:7] dmask:0xf unorm a16
|
||||
define amdgpu_ps void @store.v4f32.3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_lo, <2 x i16> %coords_hi, <4 x float> %val) {
|
||||
main_body:
|
||||
%x = extractelement <2 x i16> %coords_lo, i32 0
|
||||
%y = extractelement <2 x i16> %coords_lo, i32 1
|
||||
%z = extractelement <2 x i16> %coords_hi, i32 0
|
||||
call void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float> %val, i32 15, i16 %x, i16 %y, i16 %z, <8 x i32> %rsrc, i32 0, i32 0)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.image.store.1d.v4f32.i16(<4 x float>, i32, i16, <8 x i32>, i32, i32) #2
|
||||
declare void @llvm.amdgcn.image.store.2d.v4f32.i16(<4 x float>, i32, i16, i16, <8 x i32>, i32, i32) #2
|
||||
declare void @llvm.amdgcn.image.store.3d.v4f32.i16(<4 x float>, i32, i16, i16, i16, <8 x i32>, i32, i32) #2
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
attributes #1 = { nounwind readonly }
|
||||
@ -157,6 +157,84 @@ image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16
|
||||
// GFX8_1: image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80]
|
||||
// GFX9: image_load v[5:7], v[1:4], s[8:15] dmask:0xf tfe d16 ; encoding: [0x00,0x0f,0x01,0xf0,0x01,0x05,0x02,0x80]
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Image Load/Store: a16
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
image_load v5, v[1:2], s[8:15] unorm a16
|
||||
// GFX9: image_load v5, v[1:2], s[8:15] unorm a16 ; encoding: [0x00,0x90,0x00,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_load v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16
|
||||
// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 ; encoding: [0x00,0x93,0x00,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_load v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16
|
||||
// GFX9: image_load v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 ; encoding: [0x00,0x97,0x00,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_load v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16
|
||||
// GFX9: image_load v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x00,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v5, v[1:2], s[8:15] unorm a16
|
||||
// GFX9: image_store v5, v[1:2], s[8:15] unorm a16 ; encoding: [0x00,0x90,0x20,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16
|
||||
// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0x3 unorm a16 ; encoding: [0x00,0x93,0x20,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16
|
||||
// GFX9: image_store v[5:7], v[1:2], s[8:15] dmask:0x7 unorm a16 ; encoding: [0x00,0x97,0x20,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16
|
||||
// GFX9: image_store v[5:8], v[1:2], s[8:15] dmask:0xf unorm a16 ; encoding: [0x00,0x9f,0x20,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
/===----------------------------------------------------------------------===//
|
||||
// Image Load/Store: a16 & d16
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
image_load v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16
|
||||
// GFX9: image_load v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 ; encoding: [0x00,0x93,0x00,0xf0,0x01,0x05,0x02,0x80]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_load v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16
|
||||
// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 ; encoding: [0x00,0x97,0x00,0xf0,0x01,0x05,0x02,0x80]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_load v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16
|
||||
// GFX9: image_load v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 ; encoding: [0x00,0x9f,0x00,0xf0,0x01,0x05,0x02,0x80]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16
|
||||
// GFX9: image_store v5, v[1:2], s[8:15] dmask:0x3 unorm a16 d16 ; encoding: [0x00,0x93,0x20,0xf0,0x01,0x05,0x02,0x80]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16
|
||||
// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0x7 unorm a16 d16 ; encoding: [0x00,0x97,0x20,0xf0,0x01,0x05,0x02,0x80]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16
|
||||
// GFX9: image_store v[5:6], v[1:2], s[8:15] dmask:0xf unorm a16 d16 ; encoding: [0x00,0x9f,0x20,0xf0,0x01,0x05,0x02,0x80]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Image Load/Store: PCK variants
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -193,6 +271,11 @@ image_load_mip_pck v5, v[1:4], s[8:15] dmask:0x1 d16
|
||||
// NOVI: error: invalid operand for instruction
|
||||
// NOGFX9: error: invalid operand for instruction
|
||||
|
||||
image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 a16
|
||||
// GFX9: image_load_mip_pck v5, v[1:2], s[8:15] dmask:0x1 a16 ; encoding: [0x00,0x81,0x10,0xf0,0x01,0x05,0x02,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm
|
||||
// GCN: image_store_mip_pck v252, v2, s[12:19] dmask:0x1 unorm ; encoding: [0x00,0x11,0x2c,0xf0,0x02,0xfc,0x03,0x00]
|
||||
|
||||
@ -216,6 +299,11 @@ image_store_mip_pck v252, v[2:5], s[12:19] dmask:0x1 d16
|
||||
// NOVI: error: invalid operand for instruction
|
||||
// NOGFX9: error: invalid operand for instruction
|
||||
|
||||
image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16
|
||||
// GFX9: image_store_mip_pck v252, v[2:3], s[12:19] dmask:0x1 a16 ; encoding: [0x00,0x81,0x2c,0xf0,0x02,0xfc,0x03,0x00]
|
||||
// NOSICI: error: a16 modifier is not supported on this GPU
|
||||
// NOVI: error: a16 modifier is not supported on this GPU
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Image Sample
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user