From 8d20785e6cb695eb0d9a63c5b58d03fcbe8939b2 Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Thu, 23 Apr 2015 23:16:22 +0000
Subject: [PATCH] [PowerPC] Support register name prefixes for vector registers

Match binutils by supporting the optional register name prefix for new vector
registers ("vs" for VSX registers and "q" for QPX registers).

llvm-svn: 235665
---
 lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp | 8 ++++++++
 test/MC/PowerPC/qpx.s                         | 3 ++-
 test/MC/PowerPC/vsx.s                         | 4 ++++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 9492e1d3f66..b6f10e61079 100644
--- a/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -1219,10 +1219,18 @@ MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
       RegNo = FRegs[IntVal];
       return false;
+    } else if (Name.startswith_lower("vs") &&
+               !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
+      RegNo = VSRegs[IntVal];
+      return false;
     } else if (Name.startswith_lower("v") &&
                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
       RegNo = VRegs[IntVal];
       return false;
+    } else if (Name.startswith_lower("q") &&
+               !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
+      RegNo = QFRegs[IntVal];
+      return false;
     } else if (Name.startswith_lower("cr") &&
                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
       RegNo = CRRegs[IntVal];
diff --git a/test/MC/PowerPC/qpx.s b/test/MC/PowerPC/qpx.s
index 0ada78b1b03..a1fb2090f8f 100644
--- a/test/MC/PowerPC/qpx.s
+++ b/test/MC/PowerPC/qpx.s
@@ -1,6 +1,7 @@
 # RUN: llvm-mc -triple powerpc64-bgq-linux --show-encoding %s | FileCheck %s
 
-# FIXME: print qvflogical aliases.
+# CHECK: qvfabs 3, 5                     # encoding: [0x10,0x60,0x2a,0x10]
+         qvfabs %q3, %q5
 
 # CHECK: qvfabs 3, 5                     # encoding: [0x10,0x60,0x2a,0x10]
          qvfabs 3, 5
diff --git a/test/MC/PowerPC/vsx.s b/test/MC/PowerPC/vsx.s
index f0b82c66189..f723a3ebc1a 100644
--- a/test/MC/PowerPC/vsx.s
+++ b/test/MC/PowerPC/vsx.s
@@ -1,6 +1,10 @@
 # RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-BE %s
 # RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | FileCheck -check-prefix=CHECK-LE %s
 
+# CHECK-BE: xxswapd 7, 63                      # encoding: [0xf0,0xff,0xfa,0x56]
+# CHECK-LE: xxswapd 7, 63                      # encoding: [0x56,0xfa,0xff,0xf0]
+            xxswapd %vs7, %vs63
+
 # CHECK-BE: lxsdx 39, 5, 31                     # encoding: [0x7c,0xe5,0xfc,0x99]
 # CHECK-LE: lxsdx 39, 5, 31                     # encoding: [0x99,0xfc,0xe5,0x7c]
             lxsdx 39, 5, 31