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[mips] Print move instructions.

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"move $4, $5" is printed instead of "or $4, $5, $zero".

llvm-svn: 176455
This commit is contained in:
Akira Hatanaka 2013-03-04 22:25:01 +00:00
parent 44abaa390d
commit 8d412f5a8a
11 changed files with 44 additions and 44 deletions
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2
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -313,7 +313,7 @@ def : InstAlias<"move $dst, $src",
(DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
Requires<[HasMips64]>;
def : InstAlias<"move $dst, $src",
(OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 0>,
(OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
Requires<[HasMips64]>;
def : InstAlias<"and $rs, $rt, $imm",
(DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),

2
lib/Target/Mips/MipsInstrInfo.td
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@ -985,7 +985,7 @@ def : InstAlias<"move $dst, $src",
(ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
Requires<[NotMips64]>;
def : InstAlias<"move $dst, $src",
(OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>,
(OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
Requires<[NotMips64]>;
def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
def : InstAlias<"addu $rs, $rt, $imm",

10
test/CodeGen/Mips/alloca.ll
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@ -3,11 +3,11 @@
define i32 @twoalloca(i32 %size) nounwind {
entry:
; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
; CHECK: or $sp, $[[T0]], $zero
; CHECK: move $sp, $[[T0]]
; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
; CHECK: or $sp, $[[T2]], $zero
; CHECK: or $4, $[[T0]], $zero
; CHECK: or $4, $[[T2]], $zero
; CHECK: move $sp, $[[T2]]
; CHECK: move $4, $[[T0]]
; CHECK: move $4, $[[T2]]
%tmp1 = alloca i8, i32 %size, align 4
%add.ptr = getelementptr inbounds i8* %tmp1, i32 5
store i8 97, i8* %add.ptr, align 1
@ -29,7 +29,7 @@ define i32 @alloca2(i32 %size) nounwind {
entry:
; CHECK: alloca2
; CHECK: subu $[[T0:[0-9]+]], $sp
; CHECK: or $sp, $[[T0]], $zero
; CHECK: move $sp, $[[T0]]
%tmp1 = alloca i8, i32 %size, align 4
%0 = bitcast i8* %tmp1 to i32*

16
test/CodeGen/Mips/eh-return32.ll
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@ -25,10 +25,10 @@ entry:
; CHECK: .cfi_offset 7,
; check that stack adjustment and handler are put in $v1 and $v0.
; CHECK: or $[[R0:[a-z0-9]+]], $5, $zero
; CHECK: or $[[R1:[a-z0-9]+]], $4, $zero
; CHECK: or $3, $[[R1]], $zero
; CHECK: or $2, $[[R0]], $zero
; CHECK: move $[[R0:[a-z0-9]+]], $5
; CHECK: move $[[R1:[a-z0-9]+]], $4
; CHECK: move $3, $[[R1]]
; CHECK: move $2, $[[R0]]
; check that $a0-$a3 are restored from stack.
; CHECK: lw $4, [[offset0]]($sp)
@ -38,7 +38,7 @@ entry:
; check that stack is adjusted by $v1 and that code returns to address in $v0
; CHECK: addiu $sp, $sp, [[spoffset]]
; CHECK: or $ra, $2, $zero
; CHECK: move $ra, $2
; CHECK: jr $ra
; CHECK: addu $sp, $sp, $3
}
@ -64,8 +64,8 @@ entry:
; CHECK: .cfi_offset 7,
; check that stack adjustment and handler are put in $v1 and $v0.
; CHECK: or $3, $4, $zero
; CHECK: or $2, $5, $zero
; CHECK: move $3, $4
; CHECK: move $2, $5
; check that $a0-$a3 are restored from stack.
; CHECK: lw $4, [[offset0]]($sp)
@ -75,7 +75,7 @@ entry:
; check that stack is adjusted by $v1 and that code returns to address in $v0
; CHECK: addiu $sp, $sp, [[spoffset]]
; CHECK: or $ra, $2, $zero
; CHECK: move $ra, $2
; CHECK: jr $ra
; CHECK: addu $sp, $sp, $3
}

16
test/CodeGen/Mips/eh-return64.ll
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@ -25,10 +25,10 @@ entry:
; CHECK: .cfi_offset 7,
; check that stack adjustment and handler are put in $v1 and $v0.
; CHECK: or $[[R0:[a-z0-9]+]], $5, $zero
; CHECK: or $[[R1:[a-z0-9]+]], $4, $zero
; CHECK: or $3, $[[R1]], $zero
; CHECK: or $2, $[[R0]], $zero
; CHECK: move $[[R0:[a-z0-9]+]], $5
; CHECK: move $[[R1:[a-z0-9]+]], $4
; CHECK: move $3, $[[R1]]
; CHECK: move $2, $[[R0]]
; check that $a0-$a3 are restored from stack.
; CHECK: ld $4, [[offset0]]($sp)
@ -38,7 +38,7 @@ entry:
; check that stack is adjusted by $v1 and that code returns to address in $v0
; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: or $ra, $2, $zero
; CHECK: move $ra, $2
; CHECK: jr $ra
; CHECK: daddu $sp, $sp, $3
@ -65,8 +65,8 @@ entry:
; CHECK: .cfi_offset 7,
; check that stack adjustment and handler are put in $v1 and $v0.
; CHECK: or $3, $4, $zero
; CHECK: or $2, $5, $zero
; CHECK: move $3, $4
; CHECK: move $2, $5
; check that $a0-$a3 are restored from stack.
; CHECK: ld $4, [[offset0]]($sp)
@ -76,7 +76,7 @@ entry:
; check that stack is adjusted by $v1 and that code returns to address in $v0
; CHECK: daddiu $sp, $sp, [[spoffset]]
; CHECK: or $ra, $2, $zero
; CHECK: move $ra, $2
; CHECK: jr $ra
; CHECK: daddu $sp, $sp, $3

2
test/CodeGen/Mips/frame-address.ll
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@ -8,5 +8,5 @@ entry:
ret i8* %0
; CHECK: move $fp, $sp
; CHECK: or $2, $fp, $zero
; CHECK: move $2, $fp
}

4
test/CodeGen/Mips/gpreg-lazy-binding.ll
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@ -2,10 +2,10 @@
@g = external global i32
; CHECK: or $gp
; CHECK: move $gp
; CHECK: jalr $25
; CHECK: nop
; CHECK-NOT: or $gp
; CHECK-NOT: move $gp
; CHECK: jalr $25
define void @f0() nounwind {

12
test/CodeGen/Mips/i64arg.ll
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@ -2,8 +2,8 @@
define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
entry:
; CHECK: or $[[R1:[0-9]+]], $5, $zero
; CHECK: or $[[R0:[0-9]+]], $4, $zero
; CHECK: move $[[R1:[0-9]+]], $5
; CHECK: move $[[R0:[0-9]+]], $4
; CHECK: ori $6, ${{[0-9]+}}, 3855
; CHECK: ori $7, ${{[0-9]+}}, 22136
; CHECK: lw $25, %call16(ff1)
@ -12,16 +12,16 @@ entry:
; CHECK: lw $25, %call16(ff2)
; CHECK: lw $[[R2:[0-9]+]], 80($sp)
; CHECK: lw $[[R3:[0-9]+]], 84($sp)
; CHECK: or $4, $[[R2]], $zero
; CHECK: or $5, $[[R3]], $zero
; CHECK: move $4, $[[R2]]
; CHECK: move $5, $[[R3]]
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
; CHECK: lw $25, %call16(ff3)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R0]], 24($sp)
; CHECK: or $6, $[[R2]], $zero
; CHECK: or $7, $[[R3]], $zero
; CHECK: move $6, $[[R2]]
; CHECK: move $7, $[[R3]]
; CHECK: jalr $25
tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
ret void

16
test/CodeGen/Mips/mips64-f128.ll
View File

@ -615,8 +615,8 @@ entry:
; CHECK: select_LD:
; CHECK: movn $8, $6, $4
; CHECK: movn $9, $7, $4
; CHECK: or $2, $8, $zero
; CHECK: or $3, $9, $zero
; CHECK: move $2, $8
; CHECK: move $3, $9
define fp128 @select_LD(i32 %a, i64, fp128 %b, fp128 %c) {
entry:
@ -626,17 +626,17 @@ entry:
}
; CHECK: selectCC_LD:
; CHECK: or $[[R0:[0-9]+]], $11, $zero
; CHECK: or $[[R1:[0-9]+]], $10, $zero
; CHECK: or $[[R2:[0-9]+]], $9, $zero
; CHECK: or $[[R3:[0-9]+]], $8, $zero
; CHECK: move $[[R0:[0-9]+]], $11
; CHECK: move $[[R1:[0-9]+]], $10
; CHECK: move $[[R2:[0-9]+]], $9
; CHECK: move $[[R3:[0-9]+]], $8
; CHECK: ld $25, %call16(__gttf2)($gp)
; CHECK: jalr $25
; CHECK: slti $1, $2, 1
; CHECK: movz $[[R1]], $[[R3]], $1
; CHECK: movz $[[R0]], $[[R2]], $1
; CHECK: or $2, $[[R1]], $zero
; CHECK: or $3, $[[R0]], $zero
; CHECK: move $2, $[[R1]]
; CHECK: move $3, $[[R0]]
define fp128 @selectCC_LD(fp128 %a, fp128 %b, fp128 %c, fp128 %d) {
entry:

2
test/CodeGen/Mips/mips64-sret.ll
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@ -6,7 +6,7 @@
define void @f(%struct.S* noalias sret %agg.result) nounwind {
entry:
; CHECK: or $2, $4, $zero
; CHECK: move $2, $4
%0 = bitcast %struct.S* %agg.result to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.S* @g to i8*), i64 32, i32 4, i1 false)

6
test/CodeGen/Mips/return_address.ll
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@ -5,7 +5,7 @@ entry:
%0 = call i8* @llvm.returnaddress(i32 0)
ret i8* %0
; CHECK: or $2, $ra, $zero
; CHECK: move $2, $ra
}
define i8* @f2() nounwind {
@ -14,9 +14,9 @@ entry:
%0 = call i8* @llvm.returnaddress(i32 0)
ret i8* %0
; CHECK: or $[[R0:[0-9]+]], $ra, $zero
; CHECK: move $[[R0:[0-9]+]], $ra
; CHECK: jal
; CHECK: or $2, $[[R0]], $zero
; CHECK: move $2, $[[R0]]
}
declare i8* @llvm.returnaddress(i32) nounwind readnone