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[NFC][ARM] Make some params members instead.

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Add MachineLoopInfo and ReachingDefAnalysis as members of
LowOverheadLoop instead of passing them several times to different
methods.
This commit is contained in:
Sam Parker 2020-01-24 10:17:43 +00:00
parent d4f114dee6
commit 8d55eeb3aa
1 changed files with 15 additions and 19 deletions
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34
lib/Target/ARM/ARMLowOverheadLoops.cpp
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@ -176,6 +176,8 @@ namespace {
struct LowOverheadLoop { struct LowOverheadLoop {
MachineLoop *ML = nullptr; MachineLoop *ML = nullptr;
MachineLoopInfo *MLI = nullptr;
ReachingDefAnalysis *RDA = nullptr;
MachineFunction *MF = nullptr; MachineFunction *MF = nullptr;
MachineInstr *InsertPt = nullptr; MachineInstr *InsertPt = nullptr;
MachineInstr *Start = nullptr; MachineInstr *Start = nullptr;
@ -189,7 +191,8 @@ namespace {
bool Revert = false; bool Revert = false;
bool CannotTailPredicate = false; bool CannotTailPredicate = false;
LowOverheadLoop(MachineLoop *ML) : ML(ML) { LowOverheadLoop(MachineLoop *ML, MachineLoopInfo *MLI,
ReachingDefAnalysis *RDA) : ML(ML), MLI(MLI), RDA(RDA) {
MF = ML->getHeader()->getParent(); MF = ML->getHeader()->getParent();
} }
@ -209,19 +212,16 @@ namespace {
!CannotTailPredicate && ML->getNumBlocks() == 1; !CannotTailPredicate && ML->getNumBlocks() == 1;
} }
bool ValidateTailPredicate(MachineInstr *StartInsertPt, bool ValidateTailPredicate(MachineInstr *StartInsertPt);
ReachingDefAnalysis *RDA,
MachineLoopInfo *MLI);
// Is it safe to define LR with DLS/WLS? // Is it safe to define LR with DLS/WLS?
// LR can be defined if it is the operand to start, because it's the same // LR can be defined if it is the operand to start, because it's the same
// value, or if it's going to be equivalent to the operand to Start. // value, or if it's going to be equivalent to the operand to Start.
MachineInstr *IsSafeToDefineLR(ReachingDefAnalysis *RDA); MachineInstr *IsSafeToDefineLR();
// Check the branch targets are within range and we satisfy our // Check the branch targets are within range and we satisfy our
// restrictions. // restrictions.
void CheckLegality(ARMBasicBlockUtils *BBUtils, ReachingDefAnalysis *RDA, void CheckLegality(ARMBasicBlockUtils *BBUtils);
MachineLoopInfo *MLI);
bool FoundAllComponents() const { bool FoundAllComponents() const {
return Start && Dec && End; return Start && Dec && End;
@ -314,7 +314,7 @@ char ARMLowOverheadLoops::ID = 0;
INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME, INITIALIZE_PASS(ARMLowOverheadLoops, DEBUG_TYPE, ARM_LOW_OVERHEAD_LOOPS_NAME,
false, false) false, false)
MachineInstr *LowOverheadLoop::IsSafeToDefineLR(ReachingDefAnalysis *RDA) { MachineInstr *LowOverheadLoop::IsSafeToDefineLR() {
// We can define LR because LR already contains the same value. // We can define LR because LR already contains the same value.
if (Start->getOperand(0).getReg() == ARM::LR) if (Start->getOperand(0).getReg() == ARM::LR)
return Start; return Start;
@ -412,9 +412,7 @@ static bool IsSafeToRemove(MachineInstr *MI, ReachingDefAnalysis *RDA,
return true; return true;
} }
bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt, bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt) {
ReachingDefAnalysis *RDA,
MachineLoopInfo *MLI) {
assert(VCTP && "VCTP instruction expected but is not set"); assert(VCTP && "VCTP instruction expected but is not set");
// All predication within the loop should be based on vctp. If the block // All predication within the loop should be based on vctp. If the block
// isn't predicated on entry, check whether the vctp is within the block // isn't predicated on entry, check whether the vctp is within the block
@ -482,7 +480,7 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt,
// Especially in the case of while loops, InsertBB may not be the // Especially in the case of while loops, InsertBB may not be the
// preheader, so we need to check that the register isn't redefined // preheader, so we need to check that the register isn't redefined
// before entering the loop. // before entering the loop.
auto CannotProvideElements = [&RDA](MachineBasicBlock *MBB, auto CannotProvideElements = [this](MachineBasicBlock *MBB,
Register NumElements) { Register NumElements) {
// NumElements is redefined in this block. // NumElements is redefined in this block.
if (RDA->getReachingDef(&MBB->back(), NumElements) >= 0) if (RDA->getReachingDef(&MBB->back(), NumElements) >= 0)
@ -563,9 +561,7 @@ bool LowOverheadLoop::ValidateTailPredicate(MachineInstr *StartInsertPt,
return true; return true;
} }
void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils, void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils) {
ReachingDefAnalysis *RDA,
MachineLoopInfo *MLI) {
if (Revert) if (Revert)
return; return;
@ -598,7 +594,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils,
return; return;
} }
InsertPt = Revert ? nullptr : IsSafeToDefineLR(RDA); InsertPt = Revert ? nullptr : IsSafeToDefineLR();
if (!InsertPt) { if (!InsertPt) {
LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n"); LLVM_DEBUG(dbgs() << "ARM Loops: Unable to find safe insertion point.\n");
Revert = true; Revert = true;
@ -615,7 +611,7 @@ void LowOverheadLoop::CheckLegality(ARMBasicBlockUtils *BBUtils,
assert(ML->getBlocks().size() == 1 && assert(ML->getBlocks().size() == 1 &&
"Shouldn't be processing a loop with more than one block"); "Shouldn't be processing a loop with more than one block");
CannotTailPredicate = !ValidateTailPredicate(InsertPt, RDA, MLI); CannotTailPredicate = !ValidateTailPredicate(InsertPt);
LLVM_DEBUG(if (CannotTailPredicate) LLVM_DEBUG(if (CannotTailPredicate)
dbgs() << "ARM Loops: Couldn't validate tail predicate.\n"); dbgs() << "ARM Loops: Couldn't validate tail predicate.\n");
} }
@ -750,7 +746,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
return nullptr; return nullptr;
}; };
LowOverheadLoop LoLoop(ML); LowOverheadLoop LoLoop(ML, MLI, RDA);
// Search the preheader for the start intrinsic. // Search the preheader for the start intrinsic.
// FIXME: I don't see why we shouldn't be supporting multiple predecessors // FIXME: I don't see why we shouldn't be supporting multiple predecessors
// with potentially multiple set.loop.iterations, so we need to enable this. // with potentially multiple set.loop.iterations, so we need to enable this.
@ -805,7 +801,7 @@ bool ARMLowOverheadLoops::ProcessLoop(MachineLoop *ML) {
LoLoop.ToRemove.insert(Remove.begin(), Remove.end()); LoLoop.ToRemove.insert(Remove.begin(), Remove.end());
} }
LoLoop.CheckLegality(BBUtils.get(), RDA, MLI); LoLoop.CheckLegality(BBUtils.get());
Expand(LoLoop); Expand(LoLoop);
return true; return true;
} }