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[WebAssembly] Tidy up let
statements in .td files (NFC)
Summary: - Delete {} for one-line `let` statements - Don't indent within `let` blocks - Add comments after `let` block's closing braces Reviewers: tlively Subscribers: dschuff, sbc100, jgravelle-google, sunfish, jfb, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57730 llvm-svn: 353248
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@ -748,10 +748,9 @@ multiclass TerRMWPattern<PatFrag rmw_32, PatFrag rmw_64, NI inst_32,
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def : TerRMWPatExternSymOffOnly<i64, rmw_64, inst_64>;
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}
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let Predicates = [HasAtomics] in {
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let Predicates = [HasAtomics] in
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defm : TerRMWPattern<atomic_cmp_swap_32, atomic_cmp_swap_64,
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ATOMIC_RMW_CMPXCHG_I32, ATOMIC_RMW_CMPXCHG_I64>;
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} // Predicates = [HasAtomics]
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// Truncating & zero-extending ternary RMW patterns.
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// DAG legalization & optimization before instruction selection may introduce
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@ -885,13 +884,12 @@ multiclass TerRMWTruncExtPattern<
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def : TerRMWPatExternSymOffOnly<i64, sext_ter_rmw_16_64<rmw_16>, inst16_64>;
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}
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let Predicates = [HasAtomics] in {
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let Predicates = [HasAtomics] in
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defm : TerRMWTruncExtPattern<
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atomic_cmp_swap_8, atomic_cmp_swap_16, atomic_cmp_swap_32, atomic_cmp_swap_64,
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ATOMIC_RMW8_U_CMPXCHG_I32, ATOMIC_RMW16_U_CMPXCHG_I32,
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ATOMIC_RMW8_U_CMPXCHG_I64, ATOMIC_RMW16_U_CMPXCHG_I64,
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ATOMIC_RMW32_U_CMPXCHG_I64>;
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}
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//===----------------------------------------------------------------------===//
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// Atomic wait / notify
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@ -21,7 +21,7 @@ defm ADJCALLSTACKDOWN : NRI<(outs), (ins i32imm:$amt, i32imm:$amt2),
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[(WebAssemblycallseq_start timm:$amt, timm:$amt2)]>;
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defm ADJCALLSTACKUP : NRI<(outs), (ins i32imm:$amt, i32imm:$amt2),
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[(WebAssemblycallseq_end timm:$amt, timm:$amt2)]>;
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} // isCodeGenOnly = 1
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} // Uses = [SP32, SP64], Defs = [SP32, SP64], isCodeGenOnly = 1
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multiclass CALL<WebAssemblyRegClass vt, string prefix> {
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defm CALL_#vt : I<(outs vt:$dst), (ins function32_op:$callee, variable_ops),
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@ -31,13 +31,12 @@ multiclass CALL<WebAssemblyRegClass vt, string prefix> {
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!strconcat(prefix, "call\t$callee"),
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0x10>;
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let isCodeGenOnly = 1 in {
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defm PCALL_INDIRECT_#vt : I<(outs vt:$dst), (ins I32:$callee, variable_ops),
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(outs), (ins I32:$callee),
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[(set vt:$dst, (WebAssemblycall1 I32:$callee))],
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"PSEUDO CALL INDIRECT\t$callee",
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"PSEUDO CALL INDIRECT\t$callee">;
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} // isCodeGenOnly = 1
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let isCodeGenOnly = 1 in
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defm PCALL_INDIRECT_#vt : I<(outs vt:$dst), (ins I32:$callee, variable_ops),
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(outs), (ins I32:$callee),
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[(set vt:$dst, (WebAssemblycall1 I32:$callee))],
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"PSEUDO CALL INDIRECT\t$callee",
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"PSEUDO CALL INDIRECT\t$callee">;
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defm CALL_INDIRECT_#vt : I<(outs vt:$dst),
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(ins TypeIndex:$type, i32imm:$flags, variable_ops),
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@ -59,16 +58,15 @@ multiclass SIMD_CALL<ValueType vt, string prefix> {
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0x10>,
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Requires<[HasSIMD128]>;
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let isCodeGenOnly = 1 in {
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defm PCALL_INDIRECT_#vt : I<(outs V128:$dst),
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(ins I32:$callee, variable_ops),
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(outs), (ins I32:$callee),
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[(set (vt V128:$dst),
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(WebAssemblycall1 I32:$callee))],
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"PSEUDO CALL INDIRECT\t$callee",
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"PSEUDO CALL INDIRECT\t$callee">,
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let isCodeGenOnly = 1 in
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defm PCALL_INDIRECT_#vt : I<(outs V128:$dst),
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(ins I32:$callee, variable_ops),
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(outs), (ins I32:$callee),
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[(set (vt V128:$dst),
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(WebAssemblycall1 I32:$callee))],
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"PSEUDO CALL INDIRECT\t$callee",
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"PSEUDO CALL INDIRECT\t$callee">,
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Requires<[HasSIMD128]>;
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} // isCodeGenOnly = 1
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defm CALL_INDIRECT_#vt : I<(outs V128:$dst),
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(ins TypeIndex:$type, i32imm:$flags, variable_ops),
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@ -77,44 +75,43 @@ multiclass SIMD_CALL<ValueType vt, string prefix> {
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!strconcat(prefix, "call_indirect\t$dst"),
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!strconcat(prefix, "call_indirect\t$type"),
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0x11>,
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Requires<[HasSIMD128]>;
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Requires<[HasSIMD128]>;
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}
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let Uses = [SP32, SP64], isCall = 1 in {
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defm "" : CALL<I32, "i32.">;
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defm "" : CALL<I64, "i64.">;
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defm "" : CALL<F32, "f32.">;
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defm "" : CALL<F64, "f64.">;
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defm "" : CALL<EXCEPT_REF, "except_ref.">;
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defm "" : SIMD_CALL<v16i8, "v128.">;
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defm "" : SIMD_CALL<v8i16, "v128.">;
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defm "" : SIMD_CALL<v4i32, "v128.">;
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defm "" : SIMD_CALL<v2i64, "v128.">;
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defm "" : SIMD_CALL<v4f32, "v128.">;
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defm "" : SIMD_CALL<v2f64, "v128.">;
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defm "" : CALL<I32, "i32.">;
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defm "" : CALL<I64, "i64.">;
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defm "" : CALL<F32, "f32.">;
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defm "" : CALL<F64, "f64.">;
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defm "" : CALL<EXCEPT_REF, "except_ref.">;
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defm "" : SIMD_CALL<v16i8, "v128.">;
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defm "" : SIMD_CALL<v8i16, "v128.">;
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defm "" : SIMD_CALL<v4i32, "v128.">;
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defm "" : SIMD_CALL<v2i64, "v128.">;
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defm "" : SIMD_CALL<v4f32, "v128.">;
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defm "" : SIMD_CALL<v2f64, "v128.">;
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let IsCanonical = 1 in {
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defm CALL_VOID : I<(outs), (ins function32_op:$callee, variable_ops),
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(outs), (ins function32_op:$callee),
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[(WebAssemblycall0 (i32 imm:$callee))],
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"call \t$callee", "call\t$callee", 0x10>;
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let IsCanonical = 1 in {
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defm CALL_VOID : I<(outs), (ins function32_op:$callee, variable_ops),
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(outs), (ins function32_op:$callee),
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[(WebAssemblycall0 (i32 imm:$callee))],
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"call \t$callee", "call\t$callee", 0x10>;
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let isCodeGenOnly = 1 in {
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defm PCALL_INDIRECT_VOID : I<(outs), (ins I32:$callee, variable_ops),
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(outs), (ins I32:$callee),
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[(WebAssemblycall0 I32:$callee)],
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"PSEUDO CALL INDIRECT\t$callee",
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"PSEUDO CALL INDIRECT\t$callee">;
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} // isCodeGenOnly = 1
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let isCodeGenOnly = 1 in
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defm PCALL_INDIRECT_VOID : I<(outs), (ins I32:$callee, variable_ops),
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(outs), (ins I32:$callee),
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[(WebAssemblycall0 I32:$callee)],
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"PSEUDO CALL INDIRECT\t$callee",
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"PSEUDO CALL INDIRECT\t$callee">;
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defm CALL_INDIRECT_VOID : I<(outs),
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(ins TypeIndex:$type, i32imm:$flags,
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variable_ops),
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(outs), (ins TypeIndex:$type, i32imm:$flags),
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[],
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"call_indirect\t", "call_indirect\t$type",
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0x11>;
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}
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defm CALL_INDIRECT_VOID : I<(outs),
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(ins TypeIndex:$type, i32imm:$flags,
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variable_ops),
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(outs), (ins TypeIndex:$type, i32imm:$flags),
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[],
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"call_indirect\t", "call_indirect\t$type",
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0x11>;
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} // IsCanonical = 1
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} // Uses = [SP32,SP64], isCall = 1
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// Patterns for matching a direct call to a global address.
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@ -20,11 +20,10 @@ defm BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
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let isCodeGenOnly = 1 in
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defm BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond),
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(outs), (ins bb_op:$dst), []>;
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let isBarrier = 1 in {
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let isBarrier = 1 in
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defm BR : NRI<(outs), (ins bb_op:$dst),
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[(br bb:$dst)],
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"br \t$dst", 0x0c>;
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} // isBarrier = 1
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} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
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def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
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@ -35,14 +34,11 @@ def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
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// A list of branch targets enclosed in {} and separated by comma.
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// Used by br_table only.
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def BrListAsmOperand : AsmOperandClass { let Name = "BrList"; }
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let OperandNamespace = "WebAssembly" in {
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let OperandType = "OPERAND_BRLIST" in {
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let OperandNamespace = "WebAssembly", OperandType = "OPERAND_BRLIST" in
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def brlist : Operand<i32> {
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let ParserMatchClass = BrListAsmOperand;
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let PrintMethod = "printBrList";
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}
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} // OPERAND_BRLIST
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} // OperandNamespace = "WebAssembly"
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// TODO: SelectionDAG's lowering insists on using a pointer as the index for
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// jump tables, so in practice we don't ever use BR_TABLE_I64 in wasm32 mode
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@ -82,9 +78,8 @@ defm END_BLOCK : NRI<(outs), (ins), [], "end_block", 0x0b>;
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defm END_LOOP : NRI<(outs), (ins), [], "end_loop", 0x0b>;
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defm END_IF : NRI<(outs), (ins), [], "end_if", 0x0b>;
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// Generic instruction, for disassembler.
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let IsCanonical = 1 in {
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let IsCanonical = 1 in
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defm END : NRI<(outs), (ins), [], "end", 0x0b>;
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}
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let isTerminator = 1, isBarrier = 1 in
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defm END_FUNCTION : NRI<(outs), (ins), [], "end_function", 0x0b>;
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} // Uses = [VALUE_STACK], Defs = [VALUE_STACK]
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@ -109,7 +104,7 @@ multiclass SIMD_RETURN<ValueType vt> {
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let isCodeGenOnly = 1 in
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defm FALLTHROUGH_RETURN_#vt : I<(outs), (ins V128:$val), (outs), (ins),
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[]>,
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Requires<[HasSIMD128]>;
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Requires<[HasSIMD128]>;
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}
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let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
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@ -187,4 +182,4 @@ let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
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[(catchret bb:$dst, bb:$from)], "catchret", 0>;
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} // isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
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// isPseudo = 1, isEHScopeReturn = 1
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}
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} // Predicates = [HasExceptionHandling]
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@ -159,11 +159,10 @@ def event_op : Operand<i32>;
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} // OperandType = "OPERAND_P2ALIGN"
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let OperandType = "OPERAND_SIGNATURE" in {
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let OperandType = "OPERAND_SIGNATURE" in
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def Signature : Operand<i32> {
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let PrintMethod = "printWebAssemblySignatureOperand";
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}
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} // OperandType = "OPERAND_SIGNATURE"
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let OperandType = "OPERAND_TYPEINDEX" in
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def TypeIndex : Operand<i32>;
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@ -194,8 +193,8 @@ include "WebAssemblyInstrFormats.td"
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//===----------------------------------------------------------------------===//
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multiclass ARGUMENT<WebAssemblyRegClass reg, ValueType vt> {
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let hasSideEffects = 1, isCodeGenOnly = 1,
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Defs = []<Register>, Uses = [ARGUMENTS] in
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let hasSideEffects = 1, isCodeGenOnly = 1, Defs = []<Register>,
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Uses = [ARGUMENTS] in
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defm ARGUMENT_#vt :
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I<(outs reg:$res), (ins i32imm:$argno), (outs), (ins i32imm:$argno),
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[(set (vt reg:$res), (WebAssemblyargument timm:$argno))]>;
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@ -209,7 +208,7 @@ defm "": ARGUMENT<EXCEPT_REF, ExceptRef>;
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// local.get and local.set are not generated by instruction selection; they
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// are implied by virtual register uses and defs.
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multiclass LOCAL<WebAssemblyRegClass vt> {
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let hasSideEffects = 0 in {
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let hasSideEffects = 0 in {
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// COPY is not an actual instruction in wasm, but since we allow local.get and
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// local.set to be implicit during most of codegen, we can have a COPY which
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// is actually a no-op because all the work is done in the implied local.get
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@ -94,7 +94,7 @@ def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
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// Constant: v128.const
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multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
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let isMoveImm = 1, isReMaterializable = 1,
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Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
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Predicates = [HasSIMD128, HasUnimplementedSIMD128] in
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defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
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[(set V128:$dst, (vec_t pat))],
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"v128.const\t$dst, "#args,
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@ -125,14 +125,13 @@ defm "" : ConstVec<v8i16,
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ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
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ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
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"$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
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let IsCanonical = 1 in {
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let IsCanonical = 1 in
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defm "" : ConstVec<v4i32,
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(ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
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vec_i32imm_op:$i2, vec_i32imm_op:$i3),
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(build_vector (i32 imm:$i0), (i32 imm:$i1),
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(i32 imm:$i2), (i32 imm:$i3)),
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"$i0, $i1, $i2, $i3">;
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}
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defm "" : ConstVec<v2i64,
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(ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
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(build_vector (i64 imm:$i0), (i64 imm:$i1)),
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