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[GlobalISel][Legalizer] Convert the FP constants to the right APFloat type for G_FCONSTANT.
We weren't converting the immediate ConstantFP during legalization, which caused the wrong bit patterns to be emitted for half type FP constants. Fixes PR36106. llvm-svn: 323582
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@ -715,7 +715,24 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
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}
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case TargetOpcode::G_FCONSTANT: {
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unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
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MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
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const ConstantFP *CFP = MI.getOperand(1).getFPImm();
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APFloat Val = CFP->getValueAPF();
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LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
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auto LLT2Sem = [](LLT Ty) {
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switch (Ty.getSizeInBits()) {
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case 32:
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return &APFloat::IEEEsingle();
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break;
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case 64:
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return &APFloat::IEEEdouble();
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break;
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default:
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llvm_unreachable("Unhandled fp widen type");
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}
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};
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bool LosesInfo;
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Val.convert(*LLT2Sem(WideTy), APFloat::rmTowardZero, &LosesInfo);
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MIRBuilder.buildFConstant(DstExt, *ConstantFP::get(Ctx, Val));
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MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
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MI.eraseFromParent();
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return Legalized;
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@ -75,7 +75,7 @@ body: |
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; CHECK: %w0 = COPY [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
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; CHECK: %x0 = COPY [[C1]](s64)
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT half 0xH0000
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; CHECK: [[C2:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
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; CHECK: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[C2]](s32)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FPTRUNC]](s16)
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; CHECK: %w0 = COPY [[ANYEXT]](s32)
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