RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 05:01:59 +01:00
Code Issues Projects Releases Wiki Activity

AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()

Browse Source 
No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

llvm-svn: 241816
This commit is contained in:
Tom Stellard 2015-07-09 16:30:27 +00:00
parent bc80c9fa30
commit 8d7c9eb6f3
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -1625,7 +1625,10 @@ bool SIInstrInfo::isOperandLegal(const MachineInstr *MI, unsigned OpIdx,
if (MO->isReg()) {
assert(DefinedRC);
const TargetRegisterClass *RC = MRI.getRegClass(MO->getReg());
const TargetRegisterClass *RC =
TargetRegisterInfo::isVirtualRegister(MO->getReg()) ?
MRI.getRegClass(MO->getReg()) :
RI.getPhysRegClass(MO->getReg());
// In order to be legal, the common sub-class must be equal to the
// class of the current operand. For example: