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[mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions
Differential Revision: http://reviews.llvm.org/D12628 llvm-svn: 251510
This commit is contained in:
Hrvoje Varga
parent
147810b739
commit
8d920d687c
@ -286,6 +286,11 @@ static DecodeStatus DecodeSyncI(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSynciR6(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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@ -1300,6 +1305,21 @@ static DecodeStatus DecodeSyncI(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSynciR6(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int Immediate = SignExtend32<16>(Insn & 0xffff);
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unsigned Base = fieldFromInstruction(Insn, 16, 5);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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Inst.addOperand(MCOperand::createReg(Base));
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Inst.addOperand(MCOperand::createImm(Immediate));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
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@ -228,6 +228,69 @@ class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
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let Inst{9-0} = funct;
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}
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class POOL32A_PAUSE_FM_MMR6<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = 0;
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let Inst{20-16} = 0;
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let Inst{15-11} = op;
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let Inst{10-6} = 0;
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let Inst{5-0} = 0;
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}
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class POOL32A_RDPGPR_FM_MMR6<bits<10> funct> {
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bits<5> rt;
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bits<5> rd;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rd;
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let Inst{15-6} = funct;
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let Inst{5-0} = 0b111100;
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}
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class POOL32A_RDHWR_FM_MMR6 {
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bits<5> rt;
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bits<5> rs;
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bits<3> sel;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = rt;
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let Inst{20-16} = rs;
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let Inst{15-14} = 0;
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let Inst{13-11} = sel;
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let Inst{10} = 0;
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let Inst{9-0} = 0b0111000000;
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}
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class POOL32A_SYNC_FM_MMR6 {
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bits<5> stype;
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bits<32> Inst;
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let Inst{31-26} = 0;
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let Inst{25-21} = 0;
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let Inst{20-16} = stype;
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let Inst{15-6} = 0b0110101101;
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let Inst{5-0} = 0b111100;
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}
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class POOL32I_SYNCI_FM_MMR6 {
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bits<21> addr;
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bits<5> base = addr{20-16};
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bits<16> immediate = addr{15-0};
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bits<32> Inst;
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let Inst{31-26} = 0b010000;
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let Inst{25-21} = 0b01100;
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let Inst{20-16} = base;
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let Inst{15-0} = immediate;
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}
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class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
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bits<5> rs;
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bits<5> rt;
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@ -82,6 +82,14 @@ class LB_MMR6_ENC : LB32_FM_MMR6;
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class LBU_MMR6_ENC : LBU32_FM_MMR6;
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class LBE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b100>;
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class LBUE_MMR6_ENC : POOL32C_LB_LBU_FM_MMR6<0b000>;
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class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
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class RDHWR_MMR6_ENC : POOL32A_RDHWR_FM_MMR6;
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class WAIT_MMR6_ENC : WAIT_FM_MM, MMR6Arch<"wait">;
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class SSNOP_MMR6_ENC : BARRIER_FM_MM<0x1>, MMR6Arch<"ssnop">;
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class SYNC_MMR6_ENC : POOL32A_SYNC_FM_MMR6;
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class SYNCI_MMR6_ENC : POOL32I_SYNCI_FM_MMR6, MMR6Arch<"synci">;
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class RDPGPR_MMR6_ENC : POOL32A_RDPGPR_FM_MMR6<0b1110000101>;
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class SDBBP_MMR6_ENC : SDBBP_FM_MM, MMR6Arch<"sdbbp">;
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class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>;
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class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>;
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class ABS_S_MMR6_ENC : POOL32F_ABS_FM_MMR6<"abs.s", 0, 0b0001101>;
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@ -441,6 +449,18 @@ class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd>
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class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>;
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class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>;
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class PAUSE_MMR6_DESC : Barrier<"pause">;
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class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel);
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string AsmString = !strconcat("rdhwr", "\t$rt, $rs, $sel");
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list<dag> Pattern = [];
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InstrItinClass Itinerary = II_RDHWR;
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Format Form = FrmR;
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}
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class WAIT_MMR6_DESC : WaitMM<"wait">;
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class SSNOP_MMR6_DESC : Barrier<"ssnop">;
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class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>;
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class DIV_MMR6_DESC : ArithLogicR<"div", GPR32Opnd>;
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class DIVU_MMR6_DESC : ArithLogicR<"divu", GPR32Opnd>;
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@ -768,6 +788,32 @@ class LUI_MMR6_DESC : IsAsCheapAsAMove, MMR6Arch<"lui">, MipsR6Inst{
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Format Form = FrmI;
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}
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class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst {
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dag OutOperandList = (outs);
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dag InOperandList = (ins i32imm:$stype);
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string AsmString = !strconcat("sync", "\t$stype");
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list<dag> Pattern = [(MipsSync imm:$stype)];
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InstrItinClass Itinerary = NoItinerary;
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bit HasSideEffects = 1;
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}
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class SYNCI_MMR6_DESC : SYNCI_FT<"synci"> {
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let DecoderMethod = "DecodeSynciR6";
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}
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class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst {
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dag OutOperandList = (outs GPR32Opnd:$rt);
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dag InOperandList = (ins GPR32Opnd:$rd);
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string AsmString = !strconcat("rdpgpr", "\t$rt, $rd");
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}
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class SDBBP_MMR6_DESC : MipsR6Inst {
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dag OutOperandList = (outs);
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dag InOperandList = (ins uimm20:$code_);
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string AsmString = !strconcat("sdbbp", "\t$code_");
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list<dag> Pattern = [];
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}
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//===----------------------------------------------------------------------===//
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//
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// Instruction Definitions
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@ -857,6 +903,15 @@ def LB_MMR6 : R6MMR6Rel, LB_MMR6_ENC, LB_MMR6_DESC, ISA_MICROMIPS32R6;
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def LBU_MMR6 : R6MMR6Rel, LBU_MMR6_ENC, LBU_MMR6_DESC, ISA_MICROMIPS32R6;
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def LBE_MMR6 : R6MMR6Rel, LBE_MMR6_ENC, LBE_MMR6_DESC, ISA_MICROMIPS32R6;
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def LBUE_MMR6 : R6MMR6Rel, LBUE_MMR6_ENC, LBUE_MMR6_DESC, ISA_MICROMIPS32R6;
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def PAUSE_MMR6 : StdMMR6Rel, PAUSE_MMR6_DESC, PAUSE_MMR6_ENC, ISA_MICROMIPS32R6;
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def RDHWR_MMR6 : R6MMR6Rel, RDHWR_MMR6_DESC, RDHWR_MMR6_ENC, ISA_MICROMIPS32R6;
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def WAIT_MMR6 : StdMMR6Rel, WAIT_MMR6_DESC, WAIT_MMR6_ENC, ISA_MICROMIPS32R6;
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def SSNOP_MMR6 : StdMMR6Rel, SSNOP_MMR6_DESC, SSNOP_MMR6_ENC, ISA_MICROMIPS32R6;
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def SYNC_MMR6 : StdMMR6Rel, SYNC_MMR6_DESC, SYNC_MMR6_ENC, ISA_MICROMIPS32R6;
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def SYNCI_MMR6 : StdMMR6Rel, SYNCI_MMR6_DESC, SYNCI_MMR6_ENC, ISA_MICROMIPS32R6;
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def RDPGPR_MMR6 : R6MMR6Rel, RDPGPR_MMR6_DESC, RDPGPR_MMR6_ENC,
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ISA_MICROMIPS32R6;
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def SDBBP_MMR6 : R6MMR6Rel, SDBBP_MMR6_DESC, SDBBP_MMR6_ENC, ISA_MICROMIPS32R6;
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def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6;
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def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6;
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let DecoderMethod = "DecodeMemMMImm16" in {
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@ -1015,3 +1070,8 @@ def B_MMR6_Pseudo : MipsAsmPseudoInst<(outs), (ins brtarget_mm:$offset),
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!strconcat("b", "\t$offset")> {
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string DecoderNamespace = "MicroMipsR6";
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}
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def : MipsInstAlias<"sync", (SYNC_MMR6 0), 1>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"sdbbp", (SDBBP_MMR6 0), 1>, ISA_MICROMIPS32R6;
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def : MipsInstAlias<"rdhwr $rt, $rs",
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(RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0), 1>,
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ISA_MICROMIPS32R6;
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@ -952,11 +952,15 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
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def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>;
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def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM;
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def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM;
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def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
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}
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let DecoderNamespace = "MicroMips" in {
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def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>,
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RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6;
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}
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let Predicates = [InMicroMips] in {
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//===----------------------------------------------------------------------===//
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@ -731,7 +731,9 @@ def PREF_R6 : R6MMR6Rel, PREF_ENC, PREF_DESC, ISA_MIPS32R6;
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def RINT_D : RINT_D_ENC, RINT_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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def RINT_S : RINT_S_ENC, RINT_S_DESC, ISA_MIPS32R6, HARDFLOAT;
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def SC_R6 : SC_R6_ENC, SC_R6_DESC, ISA_MIPS32R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SDBBP_R6 : SDBBP_R6_ENC, SDBBP_R6_DESC, ISA_MIPS32R6;
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}
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def SDC2_R6 : SDC2_R6_ENC, SDC2_R6_DESC, ISA_MIPS32R6;
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def SELEQZ : R6MMR6Rel, SELEQZ_ENC, SELEQZ_DESC, ISA_MIPS32R6, GPR_32;
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def SELEQZ_D : SELEQZ_D_ENC, SELEQZ_D_DESC, ISA_MIPS32R6, HARDFLOAT;
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@ -749,7 +751,9 @@ def SWC2_R6 : SWC2_R6_ENC, SWC2_R6_DESC, ISA_MIPS32R6;
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//
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//===----------------------------------------------------------------------===//
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6;
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}
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def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6;
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//===----------------------------------------------------------------------===//
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@ -1338,8 +1338,8 @@ let DecoderNamespace = "COP3_" in {
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}
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}
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def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
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def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
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def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
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def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
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let AdditionalPredicates = [NotInMicroMips] in {
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def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
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@ -1571,9 +1571,9 @@ def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
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0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
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0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
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let AdditionalPredicates = [NotInMicroMips] in {
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def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
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}
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def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
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def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
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@ -1585,9 +1585,9 @@ def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
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class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
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FrmOther, asmstr>;
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def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
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def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop">, BARRIER_FM<1>;
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def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
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def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
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def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
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// JR_HB and JALR_HB are defined here using the new style naming
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// scheme because some of this code is shared with Mips32r6InstrInfo.td
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@ -218,3 +218,15 @@
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0x14 0x85 0x00 0x08 # CHECK: lbu $4, 8($5)
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0x60 0x85 0x68 0x08 # CHECK: lbe $4, 8($5)
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0x60 0x85 0x60 0x08 # CHECK: lbue $4, 8($5)
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0x00 0x00 0x28 0x00 # CHECK: pause
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0x00 0xbd 0x11 0xc0 # CHECK: rdhwr $5, $29, 2
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0x00 0xbd 0x01 0xc0 # CHECK: rdhwr $5, $29
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0x00 0x00 0x93 0x7c # CHECK: wait
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0x00 0x11 0x93 0x7c # CHECK: wait 17
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0x00 0x00 0x08 0x00 # CHECK: ssnop
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0x00 0x00 0x6b 0x7c # CHECK: sync
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0x00 0x11 0x6b 0x7c # CHECK: sync 17
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0x41 0x85 0x00 0x08 # CHECK: synci 8($5)
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0x00 0x69 0xe1 0x7c # CHECK: rdpgpr $3, $9
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0x00 0x00 0xdb 0x7c # CHECK: sdbbp
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0x00 0x22 0xdb 0x7c # CHECK: sdbbp 34
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@ -11,10 +11,10 @@
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#------------------------------------------------------------------------------
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# CHECK-EL: sdbbp # encoding: [0x00,0x00,0x7c,0xdb]
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# CHECK-EL: sdbbp 34 # encoding: [0x22,0x00,0x7c,0xdb]
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# CHECK-EL: .set push
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# CHECK-EL: .set mips32r2
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# CHECK-EL: rdhwr $5, $29
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# CHECK-EL: .set pop # encoding: [0xbd,0x00,0x3c,0x6b]
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# CHECK-EL-NOT: .set push
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# CHECK-EL-NOT: .set mips32r2
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# CHECK-EL: rdhwr $5, $29 # encoding: [0xbd,0x00,0x3c,0x6b]
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# CHECK-EL-NOT: .set pop
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# CHECK-EL: cache 1, 8($5) # encoding: [0x25,0x20,0x08,0x60]
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# CHECK-EL: pref 1, 8($5) # encoding: [0x25,0x60,0x08,0x20]
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# CHECK-EL: ssnop # encoding: [0x00,0x00,0x00,0x08]
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@ -53,10 +53,10 @@
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#------------------------------------------------------------------------------
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# CHECK-EB: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
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# CHECK-EB: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
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# CHECK-EB: .set push
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# CHECK-EB: .set mips32r2
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# CHECK-EB: rdhwr $5, $29
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# CHECK-EB: .set pop # encoding: [0x00,0xbd,0x6b,0x3c]
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# CHECK-EB-NOT: .set push
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# CHECK-EB-NOT: .set mips32r2
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# CHECK-EB: rdhwr $5, $29 # encoding: [0x00,0xbd,0x6b,0x3c]
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# CHECK-EB-NOT: .set pop
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# CHECK-EB: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08]
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# CHECK-EB: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08]
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# CHECK-EB: ssnop # encoding: [0x00,0x00,0x08,0x00]
|
||||
|
||||
@ -74,6 +74,19 @@
|
||||
subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0]
|
||||
wrpgpr $3, $4 # CHECK: wrpgpr $3, $4 # encoding: [0x00,0x64,0xf1,0x7c]
|
||||
wsbh $3, $4 # CHECK: wsbh $3, $4 # encoding: [0x00,0x64,0x7b,0x3c]
|
||||
pause # CHECK: pause # encoding: [0x00,0x00,0x28,0x00]
|
||||
rdhwr $5, $29, 2 # CHECK: rdhwr $5, $29, 2 # encoding: [0x00,0xbd,0x11,0xc0]
|
||||
rdhwr $5, $29, 0 # CHECK: rdhwr $5, $29 # encoding: [0x00,0xbd,0x01,0xc0]
|
||||
rdhwr $5, $29 # CHECK: rdhwr $5, $29 # encoding: [0x00,0xbd,0x01,0xc0]
|
||||
wait # CHECK: wait # encoding: [0x00,0x00,0x93,0x7c]
|
||||
wait 17 # CHECK: wait 17 # encoding: [0x00,0x11,0x93,0x7c]
|
||||
ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x08,0x00]
|
||||
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
|
||||
sync 17 # CHECK: sync 17 # encoding: [0x00,0x11,0x6b,0x7c]
|
||||
synci 8($5) # CHECK: synci 8($5) # encoding: [0x41,0x85,0x00,0x08]
|
||||
rdpgpr $3, $9 # CHECK: $3, $9 # encoding: [0x00,0x69,0xe1,0x7c]
|
||||
sdbbp # CHECK: sdbbp # encoding: [0x00,0x00,0xdb,0x7c]
|
||||
sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x00,0x22,0xdb,0x7c]
|
||||
xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10]
|
||||
xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2]
|
||||
sw $5, 4($6) # CHECK: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user