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AMDGPU: Fix crash when disassembling VOP3 mac

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The unused dummy src2_modifiers is missing, so it crashes
when trying to print it.

I tried to fully remove src2_modifiers, but there are some
irritations in the places where it is converted to mad since
it starts to require modifying use lists while iterating over
them.

llvm-svn: 299861
This commit is contained in:
Matt Arsenault 2017-04-10 17:58:06 +00:00
parent c56ab3f3f4
commit 8dbeb825a7
11 changed files with 42 additions and 19 deletions
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1
lib/Target/AMDGPU/AMDGPU.h
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@ -11,6 +11,7 @@
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/Target/TargetMachine.h"
namespace llvm {

1
lib/Target/AMDGPU/AMDGPUInstrInfo.h
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@ -21,7 +21,6 @@
#include "Utils/AMDGPUBaseInfo.h"
#define GET_INSTRINFO_HEADER
#define GET_INSTRINFO_ENUM
#include "AMDGPUGenInstrInfo.inc"
namespace llvm {

1
lib/Target/AMDGPU/AMDGPURegisterInfo.h
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@ -19,7 +19,6 @@
#include "llvm/Target/TargetRegisterInfo.h"
#define GET_REGINFO_HEADER
#define GET_REGINFO_ENUM
#include "AMDGPUGenRegisterInfo.inc"
namespace llvm {

1
lib/Target/AMDGPU/AMDGPUSubtarget.cpp
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@ -23,7 +23,6 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-subtarget"
#define GET_SUBTARGETINFO_ENUM
#define GET_SUBTARGETINFO_TARGET_DESC
#define GET_SUBTARGETINFO_CTOR
#include "AMDGPUGenSubtargetInfo.inc"

16
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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@ -22,6 +22,7 @@
#include "AMDGPURegisterInfo.h"
#include "SIDefines.h"
#include "Utils/AMDGPUBaseInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
@ -105,10 +106,6 @@ static DecodeStatus decodeOperand_VSrcV216(MCInst &Inst,
return addOperand(Inst, DAsm->decodeOperand_VSrcV216(Imm));
}
#define GET_SUBTARGETINFO_ENUM
#include "AMDGPUGenSubtargetInfo.inc"
#undef GET_SUBTARGETINFO_ENUM
#include "AMDGPUGenDisassemblerTables.inc"
//===----------------------------------------------------------------------===//
@ -188,6 +185,17 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Res = tryDecodeInst(DecoderTableAMDGPU64, MI, QW, Address);
} while (false);
if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
MI.getOpcode() == AMDGPU::V_MAC_F32_e64_si ||
MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi)) {
// Insert dummy unused src2_modifiers.
int Src2ModIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
AMDGPU::OpName::src2_modifiers);
auto I = MI.begin();
std::advance(I, Src2ModIdx);
MI.insert(I, MCOperand::createImm(0));
}
Size = Res ? (MaxInstBytesNum - Bytes.size()) : 0;
return Res;
}

6
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@ -54,11 +54,17 @@ MCObjectWriter *createAMDGPUELFObjectWriter(bool Is64Bit,
#define GET_REGINFO_ENUM
#include "AMDGPUGenRegisterInfo.inc"
#undef GET_REGINFO_ENUM
#define GET_INSTRINFO_ENUM
#define GET_INSTRINFO_OPERAND_ENUM
#include "AMDGPUGenInstrInfo.inc"
#undef GET_INSTRINFO_OPERAND_ENUM
#undef GET_INSTRINFO_ENUM
#define GET_SUBTARGETINFO_ENUM
#include "AMDGPUGenSubtargetInfo.inc"
#undef GET_SUBTARGETINFO_ENUM
#endif

1
lib/Target/AMDGPU/SIMachineFunctionInfo.h
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@ -16,6 +16,7 @@
#include "AMDGPUMachineFunction.h"
#include "SIRegisterInfo.h"
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#include "llvm/CodeGen/PseudoSourceValue.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"

9
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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@ -36,19 +36,12 @@
#include <cstring>
#include <utility>
#define GET_SUBTARGETINFO_ENUM
#include "AMDGPUGenSubtargetInfo.inc"
#undef GET_SUBTARGETINFO_ENUM
#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
#define GET_REGINFO_ENUM
#include "AMDGPUGenRegisterInfo.inc"
#undef GET_REGINFO_ENUM
#define GET_INSTRINFO_NAMED_OPS
#define GET_INSTRINFO_ENUM
#include "AMDGPUGenInstrInfo.inc"
#undef GET_INSTRINFO_NAMED_OPS
#undef GET_INSTRINFO_ENUM
namespace {

4
lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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@ -21,10 +21,6 @@
#include <cstdint>
#include <utility>
#define GET_INSTRINFO_OPERAND_ENUM
#include "AMDGPUGenInstrInfo.inc"
#undef GET_INSTRINFO_OPERAND_ENUM
namespace llvm {
class FeatureBitset;

2
lib/Target/AMDGPU/VOP2Instructions.td
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@ -181,6 +181,8 @@ class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
def VOP_MADMK_F16 : VOP_MADMK <f16>;
def VOP_MADMK_F32 : VOP_MADMK <f32>;
// FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
// and processing time but it makes it easier to convert to mad.
class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,

19
test/MC/Disassembler/AMDGPU/mac.txt Normal file
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@ -0,0 +1,19 @@
# RUN: llvm-mc -arch=amdgcn -mcpu=tonga -disassemble -show-encoding < %s | FileCheck %s -check-prefix=VI
# VI: v_mac_f32_e64 v0, v1, v2 mul:2 ; encoding: [0x00,0x00,0x16,0xd1,0x01,0x05,0x02,0x08]
0x00 0x00 0x16 0xd1 0x01 0x05 0x02 0x08
# VI: v_mac_f32_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x00]
0x00 0x80 0x16 0xd1 0x01 0x05 0x02 0x00
# VI: v_mac_f32_e64 v0, v1, v2 clamp mul:2 ; encoding: [0x00,0x80,0x16,0xd1,0x01,0x05,0x02,0x08]
0x00 0x80 0x16 0xd1 0x01 0x05 0x02 0x08
# VI: v_mac_f16_e64 v0, v1, v2 mul:2 ; encoding: [0x00,0x00,0x23,0xd1,0x01,0x05,0x02,0x08]
0x00 0x00 0x23 0xd1 0x01 0x05 0x02 0x08
# VI: v_mac_f16_e64 v0, v1, v2 clamp ; encoding: [0x00,0x80,0x23,0xd1,0x01,0x05,0x02,0x00]
0x00 0x80 0x23 0xd1 0x01 0x05 0x02 0x00
# VI: v_mac_f16_e64 v0, v1, v2 clamp mul:2 ; encoding: [0x00,0x80,0x23,0xd1,0x01,0x05,0x02,0x08]
0x00 0x80 0x23 0xd1 0x01 0x05 0x02 0x08