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[mips] Deal with empty blocks in the mips hazard scheduler

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This patch teaches the hazard scheduler how to handle empty blocks
when search for the next real instruction when dealing with forbidden
slots.

Reviewers: slthakur

Differential Revision: https://reviews.llvm.org/D31293

llvm-svn: 299427
This commit is contained in:
Simon Dardis 2017-04-04 11:28:53 +00:00
parent c298b766f8
commit 8e08b0c3c1
2 changed files with 106 additions and 11 deletions
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25
lib/Target/Mips/MipsHazardSchedule.cpp
View File

@ -103,23 +103,24 @@ static Iter getNextMachineInstrInBB(Iter Position) {
// Find the next real instruction from the current position, looking through
// basic block boundaries.
static Iter getNextMachineInstr(Iter Position, MachineBasicBlock *Parent) {
static std::pair<Iter, bool> getNextMachineInstr(Iter Position, MachineBasicBlock * Parent) {
if (Position == Parent->end()) {
MachineBasicBlock *Succ = Parent->getNextNode();
if (Succ != nullptr && Parent->isSuccessor(Succ)) {
Position = Succ->begin();
Parent = Succ;
} else {
llvm_unreachable(
"Should have identified the end of the function earlier!");
}
do {
MachineBasicBlock *Succ = Parent->getNextNode();
if (Succ != nullptr && Parent->isSuccessor(Succ)) {
Position = Succ->begin();
Parent = Succ;
} else {
return std::make_pair(Position, true);
}
} while (Parent->empty());
}
Iter Instr = getNextMachineInstrInBB(Position);
if (Instr == Parent->end()) {
return getNextMachineInstr(Instr, Parent);
}
return Instr;
return std::make_pair(Instr, false);
}
bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
@ -145,7 +146,9 @@ bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) {
bool LastInstInFunction =
std::next(I) == FI->end() && std::next(FI) == MF.end();
if (!LastInstInFunction) {
Inst = getNextMachineInstr(std::next(I), &*FI);
std::pair<Iter, bool> Res = getNextMachineInstr(std::next(I), &*FI);
LastInstInFunction |= Res.second;
Inst = Res.first;
}
if (LastInstInFunction || !TII->SafeInForbiddenSlot(*Inst)) {

92
test/CodeGen/Mips/compactbranches/empty-block.mir Normal file
View File

@ -0,0 +1,92 @@
# RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s
# Check that empty blocks in the cfg don't cause the mips hazard scheduler to
# crash and that the nop is inserted correctly.
# CHECK: blezc
# CHECK: nop
# CHECK: # BB#1:
# CHECK: .insn
# CHECK: # BB#2:
# CHECK: .insn
# CHECK: # BB#3:
# CHECK: jal
--- |
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"
declare i32 @k()
declare void @f(i32)
define void @l5() {
entry:
%call = tail call i32 @k()
%cmp = icmp sgt i32 %call, 0
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @f(i32 signext 2)
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
---
name: l5
alignment: 2
exposesReturnsTwice: false
noVRegs: true
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 24
offsetAdjustment: 0
maxAlignment: 4
adjustsStack: true
hasCalls: true
maxCallFrameSize: 16
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
stack:
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' }
body: |
bb.0.entry:
successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000)
liveins: %ra
%sp = ADDiu %sp, -24
CFI_INSTRUCTION def_cfa_offset 24
SW killed %ra, %sp, 20 :: (store 4 into %stack.0)
CFI_INSTRUCTION offset %ra_64, -4
JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0
BLEZ %v0, %bb.4.if.end, implicit-def %at
bb.1.if.then:
successors: %bb.2.if.then(0x80000000)
bb.2.if.then:
successors: %bb.3.if.then(0x80000000)
bb.3.if.then:
successors: %bb.4.if.end(0x80000000)
%a0 = ADDiu %zero, 2
JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp
bb.4.if.end:
%ra = LW %sp, 20 :: (load 4 from %stack.0)
%sp = ADDiu %sp, 24
PseudoReturn undef %ra
...