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[x86] regenerate complete checks for test; NFC

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llvm-svn: 347051
This commit is contained in:
Sanjay Patel 2018-11-16 14:44:20 +00:00
parent e925a3458b
commit 8e40580147
1 changed files with 49 additions and 30 deletions
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79
test/CodeGen/X86/2008-09-11-CoalescerBug2.ll
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@ -1,44 +1,63 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- ; RUN: llc < %s -mtriple=i686--
; RUN: llc -pre-RA-sched=source < %s -mtriple=i686-unknown-linux -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED ; RUN: llc -pre-RA-sched=source < %s -mtriple=i686-unknown-linux -mcpu=corei7 | FileCheck %s --check-prefix=SOURCE-SCHED
; PR2748 ; PR2748
@g_73 = external global i32 ; <i32*> [#uses=1] @g_73 = external global i32
@g_5 = external global i32 ; <i32*> [#uses=1] @g_5 = external global i32
define i32 @func_44(i16 signext %p_46) nounwind { define i32 @func_44(i16 signext %p_46) nounwind {
; SOURCE-SCHED-LABEL: func_44:
; SOURCE-SCHED: # %bb.0: # %entry
; SOURCE-SCHED-NEXT: subl $12, %esp
; SOURCE-SCHED-NEXT: movl g_5, %eax
; SOURCE-SCHED-NEXT: sarl %eax
; SOURCE-SCHED-NEXT: xorl %ecx, %ecx
; SOURCE-SCHED-NEXT: cmpl $1, %eax
; SOURCE-SCHED-NEXT: setg %cl
; SOURCE-SCHED-NEXT: movb g_73, %dl
; SOURCE-SCHED-NEXT: xorl %eax, %eax
; SOURCE-SCHED-NEXT: subl {{[0-9]+}}(%esp), %eax
; SOURCE-SCHED-NEXT: testb %dl, %dl
; SOURCE-SCHED-NEXT: jne .LBB0_2
; SOURCE-SCHED-NEXT: # %bb.1: # %bb11
; SOURCE-SCHED-NEXT: movzbl %al, %eax
; SOURCE-SCHED-NEXT: # kill: def $eax killed $eax def $ax
; SOURCE-SCHED-NEXT: divb %dl
; SOURCE-SCHED-NEXT: movzbl %ah, %eax
; SOURCE-SCHED-NEXT: .LBB0_2: # %bb12
; SOURCE-SCHED-NEXT: xorl %edx, %edx
; SOURCE-SCHED-NEXT: testb %al, %al
; SOURCE-SCHED-NEXT: setne %dl
; SOURCE-SCHED-NEXT: subl $4, %esp
; SOURCE-SCHED-NEXT: pushl $0
; SOURCE-SCHED-NEXT: pushl %ecx
; SOURCE-SCHED-NEXT: pushl %edx
; SOURCE-SCHED-NEXT: calll func_48
; SOURCE-SCHED-NEXT: addl $28, %esp
; SOURCE-SCHED-NEXT: retl
entry: entry:
; SOURCE-SCHED: subl %0 = load i32, i32* @g_5, align 4
; SOURCE-SCHED: movl %1 = ashr i32 %0, 1
; SOURCE-SCHED: sarl %2 = icmp sgt i32 %1, 1
; SOURCE-SCHED: xorl %3 = zext i1 %2 to i32
; SOURCE-SCHED: cmpl %4 = load i32, i32* @g_73, align 4
; SOURCE-SCHED: setg %5 = zext i16 %p_46 to i64
; SOURCE-SCHED: movb %6 = sub i64 0, %5
; SOURCE-SCHED: xorl %7 = trunc i64 %6 to i8
; SOURCE-SCHED: subl %8 = trunc i32 %4 to i8
; SOURCE-SCHED: testb %9 = icmp eq i8 %8, 0
; SOURCE-SCHED: jne
%0 = load i32, i32* @g_5, align 4 ; <i32> [#uses=1]
%1 = ashr i32 %0, 1 ; <i32> [#uses=1]
%2 = icmp sgt i32 %1, 1 ; <i1> [#uses=1]
%3 = zext i1 %2 to i32 ; <i32> [#uses=1]
%4 = load i32, i32* @g_73, align 4 ; <i32> [#uses=1]
%5 = zext i16 %p_46 to i64 ; <i64> [#uses=1]
%6 = sub i64 0, %5 ; <i64> [#uses=1]
%7 = trunc i64 %6 to i8 ; <i8> [#uses=2]
%8 = trunc i32 %4 to i8 ; <i8> [#uses=2]
%9 = icmp eq i8 %8, 0 ; <i1> [#uses=1]
br i1 %9, label %bb11, label %bb12 br i1 %9, label %bb11, label %bb12
bb11: ; preds = %entry bb11:
%10 = urem i8 %7, %8 ; <i8> [#uses=1] %10 = urem i8 %7, %8
br label %bb12 br label %bb12
bb12: ; preds = %bb11, %entry bb12:
%.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ] ; <i8> [#uses=1] %.014.in = phi i8 [ %10, %bb11 ], [ %7, %entry ]
%11 = icmp ne i8 %.014.in, 0 ; <i1> [#uses=1] %11 = icmp ne i8 %.014.in, 0
%12 = zext i1 %11 to i32 ; <i32> [#uses=1] %12 = zext i1 %11 to i32
%13 = tail call i32 (...) @func_48( i32 %12, i32 %3, i32 0 ) nounwind ; <i32> [#uses=0] %13 = tail call i32 (...) @func_48( i32 %12, i32 %3, i32 0 ) nounwind
ret i32 undef ret i32 undef
} }