mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 20:23:11 +01:00
[RISCV] Fix up stale VECREDUCE comments. NFC.
Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D98399
This commit is contained in:
parent
bcace0dff8
commit
8e6f056201
@ -2557,9 +2557,6 @@ static unsigned getRVVReductionOp(unsigned ISDOpcode) {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Take a (supported) standard ISD reduction opcode and transform it to a RISCV
|
|
||||||
// reduction opcode. Note that this returns a vector type, which must be
|
|
||||||
// further processed to access the scalar result in element 0.
|
|
||||||
SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
|
SDValue RISCVTargetLowering::lowerVECREDUCE(SDValue Op,
|
||||||
SelectionDAG &DAG) const {
|
SelectionDAG &DAG) const {
|
||||||
SDLoc DL(Op);
|
SDLoc DL(Op);
|
||||||
@ -3634,9 +3631,6 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
|
|||||||
case ISD::VECREDUCE_UMAX:
|
case ISD::VECREDUCE_UMAX:
|
||||||
case ISD::VECREDUCE_SMIN:
|
case ISD::VECREDUCE_SMIN:
|
||||||
case ISD::VECREDUCE_UMIN:
|
case ISD::VECREDUCE_UMIN:
|
||||||
// The custom-lowering for these nodes returns a vector whose first element
|
|
||||||
// is the result of the reduction. Extract its first element and let the
|
|
||||||
// legalization for EXTRACT_VECTOR_ELT do the rest of the job.
|
|
||||||
if (SDValue V = lowerVECREDUCE(SDValue(N, 0), DAG))
|
if (SDValue V = lowerVECREDUCE(SDValue(N, 0), DAG))
|
||||||
Results.push_back(V);
|
Results.push_back(V);
|
||||||
break;
|
break;
|
||||||
|
Loading…
Reference in New Issue
Block a user