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Revert r305677 [CodeGen] Add generic MacroFusion pass.
This causes Windows buildbot failures do an ambiguous call. llvm-svn: 305681
This commit is contained in:
Florian Hahn
parent
9de5c3ed15
commit
8e7ee1f5d5
@ -1,41 +0,0 @@
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//===- MacroFusion.h - Macro Fusion ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the definition of the DAG scheduling mutation to
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/// pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include <functional>
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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namespace llvm {
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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typedef std::function<bool(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI)> ShouldSchedulePredTy;
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/// \brief Create a DAG scheduling mutation to pair instructions back to back
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/// for instructions that benefit according to the target-specific
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/// shouldScheduleAdjacent predicate function.
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std::unique_ptr<ScheduleDAGMutation>
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createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
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/// \brief Create a DAG scheduling mutation to pair branch instructions with one
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/// of their predecessors back to back for instructions that benefit according
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/// to the target-specific shouldScheduleAdjacent predicate function.
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std::unique_ptr<ScheduleDAGMutation>
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createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent);
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} // end namespace llvm
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@ -92,7 +92,6 @@ add_llvm_library(LLVMCodeGen
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PatchableFunction.cpp
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MIRPrinter.cpp
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MIRPrintingPass.cpp
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MacroFusion.cpp
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OptimizePHIs.cpp
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ParallelCG.cpp
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PeepholeOptimizer.cpp
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@ -1,150 +0,0 @@
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//===- MacroFusion.cpp - Macro Fusion ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the implementation of the DAG scheduling mutation
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/// to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define DEBUG_TYPE "misched"
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STATISTIC(NumFused, "Number of instr pairs fused");
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using namespace llvm;
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static cl::opt<bool> EnableMacroFusion("misched-fusion", cl::Hidden,
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cl::desc("Enable scheduling for macro fusion."), cl::init(true));
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namespace {
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static void fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
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SUnit &SecondSU) {
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// Create a single weak edge between the adjacent instrs. The only effect is
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// to cause bottom-up scheduling to heavily prioritize the clustered instrs.
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DAG.addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster));
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// Adjust the latency between the anchor instr and its
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// predecessors.
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for (SDep &IDep : SecondSU.Preds)
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if (IDep.getSUnit() == &FirstSU)
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IDep.setLatency(0);
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// Adjust the latency between the dependent instr and its
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// predecessors.
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for (SDep &IDep : FirstSU.Succs)
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if (IDep.getSUnit() == &SecondSU)
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IDep.setLatency(0);
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DEBUG(dbgs() << DAG.MF.getName() << "(): Macro fuse ";
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FirstSU.print(dbgs(), &DAG); dbgs() << " - ";
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SecondSU.print(dbgs(), &DAG); dbgs() << " / ";
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dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " <<
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DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n'; );
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if (&SecondSU != &DAG.ExitSU)
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// Make instructions dependent on FirstSU also dependent on SecondSU to
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// prevent them from being scheduled between FirstSU and and SecondSU.
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for (const SDep &SI : FirstSU.Succs) {
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if (SI.getSUnit() == &SecondSU)
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continue;
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DEBUG(dbgs() << " Copy Succ ";
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SI.getSUnit()->print(dbgs(), &DAG); dbgs() << '\n';);
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DAG.addEdge(SI.getSUnit(), SDep(&SecondSU, SDep::Artificial));
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}
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++NumFused;
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}
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/// \brief Post-process the DAG to create cluster edges between instrs that may
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/// be fused by the processor into a single operation.
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class MacroFusion : public ScheduleDAGMutation {
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ShouldSchedulePredTy shouldScheduleAdjacent;
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bool FuseBlock;
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bool scheduleAdjacentImpl(ScheduleDAGMI &DAG, SUnit &AnchorSU);
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public:
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MacroFusion(ShouldSchedulePredTy shouldScheduleAdjacent, bool FuseBlock)
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: shouldScheduleAdjacent(shouldScheduleAdjacent), FuseBlock(FuseBlock) {}
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void apply(ScheduleDAGInstrs *DAGInstrs) override;
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};
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void MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
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ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
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if (FuseBlock)
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// For each of the SUnits in the scheduling block, try to fuse the instr in
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// it with one in its predecessors.
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for (SUnit &ISU : DAG->SUnits)
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scheduleAdjacentImpl(*DAG, ISU);
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if (DAG->ExitSU.getInstr())
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// Try to fuse the instr in the ExitSU with one in its predecessors.
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scheduleAdjacentImpl(*DAG, DAG->ExitSU);
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}
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/// \brief Implement the fusion of instr pairs in the scheduling DAG,
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/// anchored at the instr in AnchorSU..
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bool MacroFusion::scheduleAdjacentImpl(ScheduleDAGMI &DAG, SUnit &AnchorSU) {
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const MachineInstr &AnchorMI = *AnchorSU.getInstr();
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const TargetInstrInfo &TII = *DAG.TII;
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const TargetSubtargetInfo &ST = DAG.MF.getSubtarget();
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// Check if the anchor instr may be fused.
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if (!shouldScheduleAdjacent(TII, ST, nullptr, AnchorMI))
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return false;
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// Explorer for fusion candidates among the dependencies of the anchor instr.
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for (SDep &Dep : AnchorSU.Preds) {
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// Ignore dependencies that don't enforce ordering.
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if (Dep.getKind() == SDep::Anti || Dep.getKind() == SDep::Output ||
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Dep.isWeak())
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continue;
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SUnit &DepSU = *Dep.getSUnit();
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if (DepSU.isBoundaryNode())
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continue;
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const MachineInstr *DepMI = DepSU.getInstr();
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if (!shouldScheduleAdjacent(TII, ST, DepMI, AnchorMI))
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continue;
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fuseInstructionPair(DAG, DepSU, AnchorSU);
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return true;
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}
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return false;
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}
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} // end anonymous namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation>
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createMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent) {
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if(EnableMacroFusion)
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return make_unique<MacroFusion>(shouldScheduleAdjacent, true);
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return nullptr;
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}
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std::unique_ptr<ScheduleDAGMutation>
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createBranchMacroFusionDAGMutation(ShouldSchedulePredTy shouldScheduleAdjacent) {
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if(EnableMacroFusion)
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return make_unique<MacroFusion>(shouldScheduleAdjacent, false);
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return nullptr;
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}
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} // end namespace llvm
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@ -7,27 +7,37 @@
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file contains the AArch64 implementation of the DAG scheduling
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/// mutation to pair instructions back to back.
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// \file This file contains the AArch64 implementation of the DAG scheduling mutation
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// to pair instructions back to back.
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64MacroFusion.h"
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#include "AArch64Subtarget.h"
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#include "llvm/CodeGen/MacroFusion.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define DEBUG_TYPE "misched"
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STATISTIC(NumFused, "Number of instr pairs fused");
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using namespace llvm;
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static cl::opt<bool> EnableMacroFusion("aarch64-misched-fusion", cl::Hidden,
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cl::desc("Enable scheduling for macro fusion."), cl::init(true));
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namespace {
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/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given SecondMI, when FirstMI is unspecified, then check if
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/// SecondMI may be part of a fused pair at all.
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/// \brief Verify that the instr pair, FirstMI and SecondMI, should be fused
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/// together. Given an anchor instr, when the other instr is unspecified, then
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/// check if the anchor instr may be part of a fused pair at all.
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static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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const TargetSubtargetInfo &TSI,
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const MachineInstr *FirstMI,
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const MachineInstr &SecondMI) {
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const MachineInstr *SecondMI) {
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assert((FirstMI || SecondMI) && "At least one instr must be specified");
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const AArch64InstrInfo &II = static_cast<const AArch64InstrInfo&>(TII);
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const AArch64Subtarget &ST = static_cast<const AArch64Subtarget&>(TSI);
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@ -35,7 +45,9 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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unsigned FirstOpcode =
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FirstMI ? FirstMI->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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unsigned SecondOpcode = SecondMI.getOpcode();
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unsigned SecondOpcode =
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SecondMI ? SecondMI->getOpcode()
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: static_cast<unsigned>(AArch64::INSTRUCTION_LIST_END);
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if (ST.hasArithmeticBccFusion())
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// Fuse CMN, CMP, TST followed by Bcc.
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@ -116,49 +128,158 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
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if (ST.hasFuseAES())
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// Fuse AES crypto operations.
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switch(SecondOpcode) {
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switch(FirstOpcode) {
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// AES encode.
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case AArch64::AESMCrr :
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return FirstOpcode == AArch64::AESErr ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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case AArch64::AESErr:
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return SecondOpcode == AArch64::AESMCrr ||
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SecondOpcode == AArch64::INSTRUCTION_LIST_END;
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// AES decode.
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case AArch64::AESIMCrr:
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return FirstOpcode == AArch64::AESDrr ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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case AArch64::AESDrr:
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return SecondOpcode == AArch64::AESIMCrr ||
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SecondOpcode == AArch64::INSTRUCTION_LIST_END;
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}
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if (ST.hasFuseLiterals())
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// Fuse literal generation operations.
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switch (SecondOpcode) {
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switch (FirstOpcode) {
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// PC relative address.
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case AArch64::ADDXri:
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return FirstOpcode == AArch64::ADRP ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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case AArch64::ADRP:
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return SecondOpcode == AArch64::ADDXri ||
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SecondOpcode == AArch64::INSTRUCTION_LIST_END;
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// 32 bit immediate.
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case AArch64::MOVKWi:
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return (FirstOpcode == AArch64::MOVZWi &&
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SecondMI.getOperand(3).getImm() == 16) ||
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FirstOpcode == AArch64::INSTRUCTION_LIST_END;
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// Lower and upper half of 64 bit immediate.
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case AArch64::MOVZWi:
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return (SecondOpcode == AArch64::MOVKWi &&
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SecondMI->getOperand(3).getImm() == 16) ||
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SecondOpcode == AArch64::INSTRUCTION_LIST_END;
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// Lower half of 64 bit immediate.
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case AArch64::MOVZXi:
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return (SecondOpcode == AArch64::MOVKXi &&
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SecondMI->getOperand(3).getImm() == 16) ||
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SecondOpcode == AArch64::INSTRUCTION_LIST_END;
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// Upper half of 64 bit immediate.
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case AArch64::MOVKXi:
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return FirstOpcode == AArch64::INSTRUCTION_LIST_END ||
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(FirstOpcode == AArch64::MOVZXi &&
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SecondMI.getOperand(3).getImm() == 16) ||
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(FirstMI->getOperand(3).getImm() == 32 &&
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FirstOpcode == AArch64::MOVKXi &&
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SecondMI.getOperand(3).getImm() == 48);
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return FirstMI->getOperand(3).getImm() == 32 &&
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((SecondOpcode == AArch64::MOVKXi &&
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SecondMI->getOperand(3).getImm() == 48) ||
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SecondOpcode == AArch64::INSTRUCTION_LIST_END);
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}
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return false;
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}
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/// \brief Implement the fusion of instr pairs in the scheduling DAG,
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/// anchored at the instr in AnchorSU..
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static bool scheduleAdjacentImpl(ScheduleDAGMI *DAG, SUnit &AnchorSU) {
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const MachineInstr *AnchorMI = AnchorSU.getInstr();
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if (!AnchorMI || AnchorMI->isPseudo() || AnchorMI->isTransient())
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return false;
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// If the anchor instr is the ExitSU, then consider its predecessors;
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// otherwise, its successors.
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bool Preds = (&AnchorSU == &DAG->ExitSU);
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SmallVectorImpl<SDep> &AnchorDeps = Preds ? AnchorSU.Preds : AnchorSU.Succs;
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const MachineInstr *FirstMI = Preds ? nullptr : AnchorMI;
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const MachineInstr *SecondMI = Preds ? AnchorMI : nullptr;
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// Check if the anchor instr may be fused.
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if (!shouldScheduleAdjacent(*DAG->TII, DAG->MF.getSubtarget(),
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FirstMI, SecondMI))
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return false;
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// Explorer for fusion candidates among the dependencies of the anchor instr.
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for (SDep &Dep : AnchorDeps) {
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// Ignore dependencies that don't enforce ordering.
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if (Dep.isWeak())
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continue;
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SUnit &DepSU = *Dep.getSUnit();
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// Ignore the ExitSU if the dependents are successors.
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if (!Preds && &DepSU == &DAG->ExitSU)
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continue;
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const MachineInstr *DepMI = DepSU.getInstr();
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if (!DepMI || DepMI->isPseudo() || DepMI->isTransient())
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continue;
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FirstMI = Preds ? DepMI : AnchorMI;
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SecondMI = Preds ? AnchorMI : DepMI;
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if (!shouldScheduleAdjacent(*DAG->TII, DAG->MF.getSubtarget(),
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FirstMI, SecondMI))
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continue;
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// Create a single weak edge between the adjacent instrs. The only effect is
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// to cause bottom-up scheduling to heavily prioritize the clustered instrs.
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SUnit &FirstSU = Preds ? DepSU : AnchorSU;
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SUnit &SecondSU = Preds ? AnchorSU : DepSU;
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DAG->addEdge(&SecondSU, SDep(&FirstSU, SDep::Cluster));
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// Adjust the latency between the anchor instr and its
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// predecessors/successors.
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for (SDep &IDep : AnchorDeps)
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if (IDep.getSUnit() == &DepSU)
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IDep.setLatency(0);
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// Adjust the latency between the dependent instr and its
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// successors/predecessors.
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for (SDep &IDep : Preds ? DepSU.Succs : DepSU.Preds)
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if (IDep.getSUnit() == &AnchorSU)
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IDep.setLatency(0);
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DEBUG(dbgs() << DAG->MF.getName() << "(): Macro fuse ";
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FirstSU.print(dbgs(), DAG); dbgs() << " - ";
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SecondSU.print(dbgs(), DAG); dbgs() << " / ";
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dbgs() << DAG->TII->getName(FirstMI->getOpcode()) << " - " <<
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DAG->TII->getName(SecondMI->getOpcode()) << '\n'; );
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if (&SecondSU != &DAG->ExitSU)
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// Make instructions dependent on FirstSU also dependent on SecondSU to
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// prevent them from being scheduled between FirstSU and and SecondSU.
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for (SUnit::const_succ_iterator
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SI = FirstSU.Succs.begin(), SE = FirstSU.Succs.end();
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SI != SE; ++SI) {
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if (!SI->getSUnit() || SI->getSUnit() == &SecondSU)
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continue;
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DEBUG(dbgs() << " Copy Succ ";
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SI->getSUnit()->print(dbgs(), DAG); dbgs() << '\n';);
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DAG->addEdge(SI->getSUnit(), SDep(&SecondSU, SDep::Artificial));
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}
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++NumFused;
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return true;
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}
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return false;
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}
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/// \brief Post-process the DAG to create cluster edges between instrs that may
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/// be fused by the processor into a single operation.
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class AArch64MacroFusion : public ScheduleDAGMutation {
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public:
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AArch64MacroFusion() {}
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void apply(ScheduleDAGInstrs *DAGInstrs) override;
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};
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void AArch64MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
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ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
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// For each of the SUnits in the scheduling block, try to fuse the instr in it
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// with one in its successors.
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for (SUnit &ISU : DAG->SUnits)
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scheduleAdjacentImpl(DAG, ISU);
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// Try to fuse the instr in the ExitSU with one in its predecessors.
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scheduleAdjacentImpl(DAG, DAG->ExitSU);
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}
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} // end namespace
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namespace llvm {
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std::unique_ptr<ScheduleDAGMutation> createAArch64MacroFusionDAGMutation () {
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return createMacroFusionDAGMutation(shouldScheduleAdjacent);
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return EnableMacroFusion ? make_unique<AArch64MacroFusion>() : nullptr;
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}
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} // end namespace llvm
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@ -2,18 +2,23 @@
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//
|
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// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// \fileThis file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
/// \file This file contains the AArch64 definition of the DAG scheduling
|
||||
/// mutation to pair instructions back to back.
|
||||
// This file contains the AArch64 definition of the DAG scheduling mutation
|
||||
// to pair instructions back to back.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "AArch64InstrInfo.h"
|
||||
#include "llvm/CodeGen/MachineScheduler.h"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AArch64MacroFusion - DAG post-processing to encourage fusion of macro ops.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// Note that you have to add:
|
||||
|
||||
@ -2,31 +2,39 @@
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// \file This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
/// \file This file contains the X86 implementation of the DAG scheduling
|
||||
/// mutation to pair instructions back to back.
|
||||
// This file contains the X86 implementation of the DAG scheduling mutation to
|
||||
// pair instructions back to back.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "X86MacroFusion.h"
|
||||
#include "X86Subtarget.h"
|
||||
#include "llvm/ADT/Statistic.h"
|
||||
#include "llvm/Support/CommandLine.h"
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "llvm/CodeGen/MacroFusion.h"
|
||||
|
||||
#define DEBUG_TYPE "misched"
|
||||
|
||||
STATISTIC(NumFused, "Number of instr pairs fused");
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
/// \brief Check if the instr pair, FirstMI and SecondMI, should be fused
|
||||
/// together. Given SecondMI, when FirstMI is unspecified, then check if
|
||||
/// SecondMI may be part of a fused pair at all.
|
||||
static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
|
||||
const TargetSubtargetInfo &TSI,
|
||||
const MachineInstr *FirstMI,
|
||||
const MachineInstr &SecondMI) {
|
||||
const X86Subtarget &ST = static_cast<const X86Subtarget&>(TSI);
|
||||
static cl::opt<bool> EnableMacroFusion("x86-misched-fusion", cl::Hidden,
|
||||
cl::desc("Enable scheduling for macro fusion."), cl::init(true));
|
||||
|
||||
namespace {
|
||||
|
||||
/// \brief Verify that the instruction pair, First and Second,
|
||||
/// should be scheduled back to back. If either instruction is unspecified,
|
||||
/// then verify that the other instruction may be part of a pair at all.
|
||||
static bool shouldScheduleAdjacent(const X86Subtarget &ST,
|
||||
const MachineInstr *First,
|
||||
const MachineInstr *Second) {
|
||||
// Check if this processor supports macro-fusion. Since this is a minor
|
||||
// heuristic, we haven't specifically reserved a feature. hasAVX is a decent
|
||||
// proxy for SandyBridge+.
|
||||
@ -39,10 +47,13 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
|
||||
FuseInc
|
||||
} FuseKind;
|
||||
|
||||
unsigned FirstOpcode = FirstMI
|
||||
? FirstMI->getOpcode()
|
||||
assert((First || Second) && "At least one instr must be specified");
|
||||
unsigned FirstOpcode = First
|
||||
? First->getOpcode()
|
||||
: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
|
||||
unsigned SecondOpcode = SecondMI.getOpcode();
|
||||
unsigned SecondOpcode = Second
|
||||
? Second->getOpcode()
|
||||
: static_cast<unsigned>(X86::INSTRUCTION_LIST_END);
|
||||
|
||||
switch (SecondOpcode) {
|
||||
default:
|
||||
@ -192,11 +203,69 @@ static bool shouldScheduleAdjacent(const TargetInstrInfo &TII,
|
||||
}
|
||||
}
|
||||
|
||||
/// \brief Post-process the DAG to create cluster edges between instructions
|
||||
/// that may be fused by the processor into a single operation.
|
||||
class X86MacroFusion : public ScheduleDAGMutation {
|
||||
public:
|
||||
X86MacroFusion() {}
|
||||
|
||||
void apply(ScheduleDAGInstrs *DAGInstrs) override;
|
||||
};
|
||||
|
||||
void X86MacroFusion::apply(ScheduleDAGInstrs *DAGInstrs) {
|
||||
ScheduleDAGMI *DAG = static_cast<ScheduleDAGMI*>(DAGInstrs);
|
||||
const X86Subtarget &ST = DAG->MF.getSubtarget<X86Subtarget>();
|
||||
|
||||
// For now, assume targets can only fuse with the branch.
|
||||
SUnit &ExitSU = DAG->ExitSU;
|
||||
MachineInstr *Branch = ExitSU.getInstr();
|
||||
if (!Branch || !shouldScheduleAdjacent(ST, nullptr, Branch))
|
||||
return;
|
||||
|
||||
for (SDep &PredDep : ExitSU.Preds) {
|
||||
if (PredDep.isWeak())
|
||||
continue;
|
||||
SUnit &SU = *PredDep.getSUnit();
|
||||
MachineInstr &Pred = *SU.getInstr();
|
||||
if (!shouldScheduleAdjacent(ST, &Pred, Branch))
|
||||
continue;
|
||||
|
||||
// Create a single weak edge from SU to ExitSU. The only effect is to cause
|
||||
// bottom-up scheduling to heavily prioritize the clustered SU. There is no
|
||||
// need to copy predecessor edges from ExitSU to SU, since top-down
|
||||
// scheduling cannot prioritize ExitSU anyway. To defer top-down scheduling
|
||||
// of SU, we could create an artificial edge from the deepest root, but it
|
||||
// hasn't been needed yet.
|
||||
bool Success = DAG->addEdge(&ExitSU, SDep(&SU, SDep::Cluster));
|
||||
(void)Success;
|
||||
assert(Success && "No DAG nodes should be reachable from ExitSU");
|
||||
|
||||
// Adjust latency of data deps between the nodes.
|
||||
for (SDep &PredDep : ExitSU.Preds)
|
||||
if (PredDep.getSUnit() == &SU)
|
||||
PredDep.setLatency(0);
|
||||
for (SDep &SuccDep : SU.Succs)
|
||||
if (SuccDep.getSUnit() == &ExitSU)
|
||||
SuccDep.setLatency(0);
|
||||
|
||||
++NumFused;
|
||||
DEBUG(dbgs() << DAG->MF.getName() << "(): Macro fuse ";
|
||||
SU.print(dbgs(), DAG);
|
||||
dbgs() << " - ExitSU"
|
||||
<< " / " << DAG->TII->getName(Pred.getOpcode()) << " - "
|
||||
<< DAG->TII->getName(Branch->getOpcode()) << '\n';);
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
} // end namespace
|
||||
|
||||
namespace llvm {
|
||||
|
||||
std::unique_ptr<ScheduleDAGMutation>
|
||||
createX86MacroFusionDAGMutation () {
|
||||
return createBranchMacroFusionDAGMutation(shouldScheduleAdjacent);
|
||||
return EnableMacroFusion ? make_unique<X86MacroFusion>() : nullptr;
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
@ -2,18 +2,23 @@
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// \file This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
/// \file This file contains the X86 definition of the DAG scheduling mutation
|
||||
/// to pair instructions back to back.
|
||||
// This file contains the X86 definition of the DAG scheduling mutation to pair
|
||||
// instructions back to back.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "X86InstrInfo.h"
|
||||
#include "llvm/CodeGen/MachineScheduler.h"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// X86MacroFusion - DAG post-processing to encourage fusion of macro ops.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// Note that you have to add:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user