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[AMDGPU] Simplify nested SI_END_CF
This is to replace the optimization from the SIOptimizeExecMaskingPreRA. We have less opportunities in the control flow lowering because many VGPR copies are still in place and will be removed later, but we know for sure an instruction is SI_END_CF and not just an arbitrary S_OR_B64 with EXEC. The subsequent change needs to convert s_and_saveexec into s_and and address new TODO lines in tests, then code block guarded by the -amdgpu-remove-redundant-endcf option in the pre-RA exec mask optimizer will be removed. Differential Revision: https://reviews.llvm.org/D76033
This commit is contained in:
Stanislav Mekhanoshin
parent
4560a0277a
commit
8e802d9c40
@ -51,6 +51,7 @@
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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@ -81,6 +82,7 @@ private:
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const SIInstrInfo *TII = nullptr;
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LiveIntervals *LIS = nullptr;
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MachineRegisterInfo *MRI = nullptr;
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DenseSet<const MachineInstr*> LoweredEndCf;
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const TargetRegisterClass *BoolRC = nullptr;
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unsigned AndOpc;
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@ -103,6 +105,13 @@ private:
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void combineMasks(MachineInstr &MI);
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// Skip to the next instruction, ignoring debug instructions, and trivial
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// block boundaries (blocks that have one (typically fallthrough) successor,
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// and the successor has one predecessor.
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MachineBasicBlock::iterator
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skipIgnoreExecInstsTrivialSucc(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator It) const;
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public:
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static char ID;
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@ -396,6 +405,36 @@ void SILowerControlFlow::emitLoop(MachineInstr &MI) {
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MI.eraseFromParent();
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}
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MachineBasicBlock::iterator
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SILowerControlFlow::skipIgnoreExecInstsTrivialSucc(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator It) const {
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SmallSet<const MachineBasicBlock *, 4> Visited;
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MachineBasicBlock *B = &MBB;
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do {
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if (!Visited.insert(B).second)
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return MBB.end();
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auto E = B->end();
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for ( ; It != E; ++It) {
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if (TII->mayReadEXEC(*MRI, *It))
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break;
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}
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if (It != E)
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return It;
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if (B->succ_size() != 1)
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return MBB.end();
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// If there is one trivial successor, advance to the next block.
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MachineBasicBlock *Succ = *B->succ_begin();
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It = Succ->begin();
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B = Succ;
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} while (true);
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}
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void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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@ -403,6 +442,18 @@ void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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MachineInstr *Def = MRI.getUniqueVRegDef(CFMask);
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const DebugLoc &DL = MI.getDebugLoc();
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// If the only instruction immediately following this END_CF is an another
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// END_CF in the only successor we can avoid emitting exec mask restore here.
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auto Next = skipIgnoreExecInstsTrivialSucc(MBB, std::next(MI.getIterator()));
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if (Next != MBB.end() && (Next->getOpcode() == AMDGPU::SI_END_CF ||
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LoweredEndCf.count(&*Next))) {
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LLVM_DEBUG(dbgs() << "Skip redundant "; MI.dump());
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if (LIS)
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LIS->RemoveMachineInstrFromMaps(MI);
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MI.eraseFromParent();
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return;
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}
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MachineBasicBlock::iterator InsPt =
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Def && Def->getParent() == &MBB ? std::next(MachineBasicBlock::iterator(Def))
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: MBB.begin();
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@ -410,6 +461,8 @@ void SILowerControlFlow::emitEndCf(MachineInstr &MI) {
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.addReg(Exec)
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.add(MI.getOperand(0));
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LoweredEndCf.insert(NewMI);
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if (LIS)
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LIS->ReplaceMachineInstrInMaps(MI, *NewMI);
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@ -556,5 +609,7 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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LoweredEndCf.clear();
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return true;
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}
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@ -1,10 +1,12 @@
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-remove-redundant-endcf < %s | FileCheck -enable-var-scope -check-prefixes=GCN,ALL %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-opt-exec-mask-pre-ra=0 < %s | FileCheck -enable-var-scope -check-prefixes=DISABLED,ALL %s
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; ALL-LABEL: {{^}}simple_nested_if:
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; GCN-LABEL: {{^}}simple_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9_]+]]
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; GCN: s_and_b64 exec, exec, vcc
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; TODO: this does not need to save exec, just perform the and.
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; GCN: s_and_saveexec_b64 s[{{[0-9:]+}}], vcc
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; GCN-NEXT: s_cbranch_execz [[ENDIF]]
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; GCN-NEXT: ; %bb.{{[0-9]+}}:
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; GCN: store_dword
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@ -13,9 +15,6 @@
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; GCN: ds_write_b32
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; GCN: s_endpgm
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; DISABLED: s_or_b64 exec, exec
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; DISABLED: s_or_b64 exec, exec
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define amdgpu_kernel void @simple_nested_if(i32 addrspace(1)* nocapture %arg) {
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
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@ -39,7 +38,7 @@ bb.outer.end: ; preds = %bb.outer.then, %bb.
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ret void
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}
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; ALL-LABEL: {{^}}uncollapsable_nested_if:
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; GCN-LABEL: {{^}}uncollapsable_nested_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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@ -82,7 +81,7 @@ bb.outer.end: ; preds = %bb.inner.then, %bb
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ret void
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}
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; ALL-LABEL: {{^}}nested_if_if_else:
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; GCN-LABEL: {{^}}nested_if_if_else:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF_OUTER:BB[0-9_]+]]
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_INNER:s\[[0-9:]+\]]]
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@ -128,7 +127,7 @@ bb.outer.end: ; preds = %bb, %bb.then, %b
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ret void
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}
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; ALL-LABEL: {{^}}nested_if_else_if:
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; GCN-LABEL: {{^}}nested_if_else_if:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
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; GCN-NEXT: s_xor_b64 [[SAVEEXEC_OUTER2:s\[[0-9:]+\]]], exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: s_cbranch_execz [[THEN_OUTER:BB[0-9_]+]]
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@ -151,9 +150,9 @@ bb.outer.end: ; preds = %bb, %bb.then, %b
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; GCN-NEXT: ; %bb.{{[0-9]+}}:
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; GCN: store_dword
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; GCN-NEXT: [[FLOW1]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_THEN]]
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; GCN-NEXT: {{^}}[[ENDIF_OUTER]]:
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
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; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER3]]
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; GCN-NOT: s_or_b64 exec
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; GCN-NOT: {{^.*:}}
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; GCN: ds_write_b32
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; GCN: s_endpgm
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define amdgpu_kernel void @nested_if_else_if(i32 addrspace(1)* nocapture %arg) {
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@ -191,7 +190,7 @@ bb.outer.end:
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ret void
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}
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; ALL-LABEL: {{^}}s_endpgm_unsafe_barrier:
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; GCN-LABEL: {{^}}s_endpgm_unsafe_barrier:
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; GCN: s_and_saveexec_b64 [[SAVEEXEC:s\[[0-9:]+\]]]
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; GCN-NEXT: s_cbranch_execz [[ENDIF:BB[0-9_]+]]
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; GCN-NEXT: ; %bb.{{[0-9]+}}:
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@ -216,8 +215,7 @@ bb.end: ; preds = %bb.then, %bb
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ret void
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}
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; Make sure scc liveness is updated if sor_b64 is removed
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; ALL-LABEL: {{^}}scc_liveness:
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; GCN-LABEL: {{^}}scc_liveness:
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; GCN: %bb10
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; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
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@ -229,7 +227,9 @@ bb.end: ; preds = %bb.then, %bb
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; GCN-NEXT: s_cbranch_execnz [[BB1_LOOP]]
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; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen
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; GCN: s_and_b64 exec, exec, {{vcc|s\[[0-9:]+\]}}
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; TODO: this does not need to save exec, just perform the and.
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; GCN: s_and_saveexec_b64 s[{{[0-9:]+}}], {{vcc|s\[[0-9:]+\]}}
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; GCN-NOT: s_or_b64 exec, exec
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@ -46,7 +46,6 @@ body: |
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; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %7, %4, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
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; GCN: DBG_VALUE
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; GCN: bb.4:
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; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
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@ -146,7 +145,6 @@ body: |
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; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %7, %4, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
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; GCN: bb.4:
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; GCN: successors: %bb.5(0x80000000)
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; GCN: bb.5:
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@ -246,7 +244,6 @@ body: |
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; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %7, %4, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
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; GCN: bb.4:
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; GCN: successors: %bb.5(0x80000000)
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; GCN: DBG_VALUE
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@ -347,7 +344,6 @@ body: |
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; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %7, %4, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN: [[S_BREV_B32_:%[0-9]+]]:sgpr_32 = S_BREV_B32 [[DEF]]
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; GCN: KILL [[DEF]]
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@ -450,7 +446,6 @@ body: |
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; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %7, %4, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; GCN: bb.3:
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; GCN: successors: %bb.4(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
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; GCN: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
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; GCN: [[S_BREV_B32_:%[0-9]+]]:sgpr_32 = S_BREV_B32 [[DEF]]
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; GCN: KILL [[DEF]]
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@ -749,7 +744,6 @@ body: |
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; GCN: BUFFER_STORE_DWORD_ADDR64 [[V_MOV_B32_e32_]], %7, %4, 0, 4, 0, 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
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; GCN: bb.3:
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; GCN: successors: %bb.5(0x80000000)
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; GCN: $exec = S_OR_B64 $exec, [[COPY4]], implicit-def $scc
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; GCN: S_BRANCH %bb.5
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; GCN: bb.4:
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; GCN: $exec = S_OR_B64 $exec, [[COPY2]], implicit-def $scc
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@ -58,7 +58,7 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3
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; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 1, v5
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; GFX9-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1
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; GFX9-NEXT: s_and_saveexec_b64 s[10:11], s[4:5]
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; GFX9-NEXT: s_cbranch_execz BB1_4
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; GFX9-NEXT: s_cbranch_execz BB1_3
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; GFX9-NEXT: ; %bb.1: ; %bb19
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; GFX9-NEXT: v_cvt_f32_u32_e32 v7, v6
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; GFX9-NEXT: v_and_b32_e32 v5, 0xffffff, v6
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@ -100,9 +100,7 @@ define void @lsr_order_mul24_1(i32 %arg, i32 %arg1, i32 %arg2, float addrspace(3
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; GFX9-NEXT: v_add_u32_e32 v3, v3, v6
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; GFX9-NEXT: s_andn2_b64 exec, exec, s[12:13]
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; GFX9-NEXT: s_cbranch_execnz BB1_2
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; GFX9-NEXT: ; %bb.3: ; %Flow
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; GFX9-NEXT: s_or_b64 exec, exec, s[12:13]
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; GFX9-NEXT: BB1_4: ; %Flow3
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; GFX9-NEXT: BB1_3: ; %Flow3
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; GFX9-NEXT: s_or_b64 exec, exec, s[10:11]
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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