MachineVerifier: Handle the optional def operand in a PATCHPOINT instruction.

The PATCHPOINT instructions have a single optional defined register operand,
but the machine verifier can't verify the optional defined register operands.
This commit makes sure that the machine verifier won't report an error when a
PATCHPOINT instruction doesn't have its optional defined register operand.
This change will allow us to enable the machine verifier for the code
generation tests for the patchpoint intrinsics.

Reviewers: Juergen Ributzka
llvm-svn: 244513

lib/CodeGen/MachineVerifier.cpp

@@ -822,9 +822,12 @@ void
 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
   const MachineInstr *MI = MO->getParent();
   const MCInstrDesc &MCID = MI->getDesc();
+  unsigned NumDefs = MCID.getNumDefs();
+  if (MCID.getOpcode() == TargetOpcode::PATCHPOINT)
+    NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;
 
   // The first MCID.NumDefs operands must be explicit register defines
-  if (MONum < MCID.getNumDefs()) {
+  if (MONum < NumDefs) {
     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];
     if (!MO->isReg())
       report("Explicit definition must be a register", MO, MONum);

test/CodeGen/X86/patchpoint-verifiable.mir

@@ -0,0 +1,43 @@
+# RUN: llc -mtriple=x86_64-apple-darwin -stop-after branch-folder -start-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
+# This test verifies that the machine verifier won't report an error when
+# verifying the PATCHPOINT instruction.
+
+--- |
+
+  define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
+  entry:
+    %result = tail call i64 (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.i64(i64 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
+    ret void
+  }
+
+  declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+
+...
+---
+name:            small_patchpoint_codegen
+tracksRegLiveness: true
+liveins:
+  - { reg: '%rdi' }
+  - { reg: '%rsi' }
+frameInfo:
+  hasPatchPoint: true
+  stackSize:     8
+  adjustsStack:  true
+  hasCalls:      true
+fixedStack:
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16 }
+body:
+  - id:          0
+    name:        entry
+    liveins:     [ '%rdi', '%rsi', '%rbp' ]
+    instructions:
+      - 'frame-setup PUSH64r killed %rbp, implicit-def %rsp, implicit %rsp'
+      - CFI_INSTRUCTION .cfi_def_cfa_offset 16
+      - 'CFI_INSTRUCTION .cfi_offset %rbp, -16'
+      - '%rbp = frame-setup MOV64rr %rsp'
+      - 'CFI_INSTRUCTION .cfi_def_cfa_register %rbp'
+# CHECK: PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax
+      - 'PATCHPOINT 5, 5, 0, 2, 0, %rdi, %rsi, csr_64, implicit-def dead early-clobber %r11, implicit-def %rsp, implicit-def dead %rax'
+      - '%rbp = POP64r implicit-def %rsp, implicit %rsp'
+      - RETQ
+...