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Legalizer: Add support for splitting insert_subvectors.
We handle this by spilling the whole thing to the stack and doing the insertion as a store. PR19492. This happens in real code because the vectorizer creates v2i128 when AVX is enabled. llvm-svn: 211435
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@ -570,6 +570,7 @@ private:
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void SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_FPOWI(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, SDValue &Hi);
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void SplitVecRes_LOAD(LoadSDNode *N, SDValue &Lo, SDValue &Hi);
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@ -545,6 +545,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
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case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break;
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case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break;
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case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break;
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case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break;
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case ISD::FP_ROUND_INREG: SplitVecRes_InregOp(N, Lo, Hi); break;
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case ISD::FPOWI: SplitVecRes_FPOWI(N, Lo, Hi); break;
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case ISD::INSERT_VECTOR_ELT: SplitVecRes_INSERT_VECTOR_ELT(N, Lo, Hi); break;
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@ -765,6 +766,43 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo,
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TLI.getVectorIdxTy()));
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}
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void DAGTypeLegalizer::SplitVecRes_INSERT_SUBVECTOR(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDValue Vec = N->getOperand(0);
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SDValue SubVec = N->getOperand(1);
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SDValue Idx = N->getOperand(2);
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SDLoc dl(N);
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GetSplitVector(Vec, Lo, Hi);
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// Spill the vector to the stack.
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EVT VecVT = Vec.getValueType();
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EVT SubVecVT = VecVT.getVectorElementType();
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SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
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SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr,
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MachinePointerInfo(), false, false, 0);
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// Store the new subvector into the specified index.
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SDValue SubVecPtr = GetVectorElementPointer(StackPtr, SubVecVT, Idx);
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Type *VecType = VecVT.getTypeForEVT(*DAG.getContext());
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unsigned Alignment = TLI.getDataLayout()->getPrefTypeAlignment(VecType);
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Store = DAG.getStore(Store, dl, SubVec, SubVecPtr, MachinePointerInfo(),
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false, false, 0);
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// Load the Lo part from the stack slot.
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Lo = DAG.getLoad(Lo.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
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false, false, false, 0);
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// Increment the pointer to the other part.
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unsigned IncrementSize = Lo.getValueType().getSizeInBits() / 8;
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StackPtr =
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DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
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DAG.getConstant(IncrementSize, StackPtr.getValueType()));
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// Load the Hi part from the stack slot.
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Hi = DAG.getLoad(Hi.getValueType(), dl, Store, StackPtr, MachinePointerInfo(),
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false, false, false, MinAlign(Alignment, IncrementSize));
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}
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void DAGTypeLegalizer::SplitVecRes_FPOWI(SDNode *N, SDValue &Lo,
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SDValue &Hi) {
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SDLoc dl(N);
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@ -40,3 +40,36 @@ define <32 x i16> @split32(<32 x i16> %a, <32 x i16> %b, <32 x i8> %__mask) {
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%2 = select <32 x i1> %1, <32 x i16> %a, <32 x i16> %b
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ret <32 x i16> %2
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}
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; PR19492
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define i128 @split128(<2 x i128> %a, <2 x i128> %b) {
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; SSE4-LABEL: split128:
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; SSE4: addq
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; SSE4: adcq
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; SSE4: addq
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; SSE4: adcq
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; SSE4: addq
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; SSE4: adcq
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; SSE4: ret
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; AVX1-LABEL: split128:
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; AVX1: addq
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; AVX1: adcq
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; AVX1: addq
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; AVX1: adcq
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; AVX1: addq
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; AVX1: adcq
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; AVX1: ret
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; AVX2-LABEL: split128:
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; AVX2: addq
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; AVX2: adcq
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; AVX2: addq
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; AVX2: adcq
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; AVX2: addq
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; AVX2: adcq
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; AVX2: ret
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%add = add nsw <2 x i128> %a, %b
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%rdx.shuf = shufflevector <2 x i128> %add, <2 x i128> undef, <2 x i32> <i32 undef, i32 0>
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%bin.rdx = add <2 x i128> %add, %rdx.shuf
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%e = extractelement <2 x i128> %bin.rdx, i32 1
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ret i128 %e
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}
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