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Silence compiler warnings.
llvm-svn: 106360
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parent
c016e11c53
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8f0bc55ea5
@ -2290,7 +2290,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
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"Reg operand expected");
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RegClass = OpInfo[OpIdx].RegClass;
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while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
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while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
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MI.addOperand(MCOperand::CreateReg(
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getRegisterEnum(B, RegClass, Rd,
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UseDRegPair(Opcode))));
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@ -2310,7 +2310,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
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// possible TIED_TO DPR/QPR's (ignored), then possible lane index.
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RegClass = OpInfo[0].RegClass;
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while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
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while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
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MI.addOperand(MCOperand::CreateReg(
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getRegisterEnum(B, RegClass, Rd,
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UseDRegPair(Opcode))));
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@ -2336,7 +2336,7 @@ static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
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++OpIdx;
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}
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while (OpIdx < NumOps && OpInfo[OpIdx].RegClass == RegClass) {
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while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) {
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assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 &&
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"Tied to operand expected");
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MI.addOperand(MCOperand::CreateReg(0));
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