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[AVR] Fix private label prefix

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This is a small pet peeve from me. This change makes sure the AVR backend uses
the correct private label prefix (.L) so that private labels are hidden in
avr-objdump.

Example code:

    define i8 @foo(i1 %cond) {
      br i1 %cond, label %then, label %else
    then:
      ret i8 3
    else:
      ret i8 5
    }

When compiling this:
  llc -march=avr -filetype=obj -o test.o test.ll
and then dumping it:
  avr-objdump -d test.o
You would previously get an ugly temporary label:

    00000000 <foo>:
       0:        81 70       andi       r24, 0x01    ; 1
       2:        80 30       cpi        r24, 0x00    ; 0
       4:        f9 f3       breq       .-2          ; 0x4 <foo+0x4>
       6:        83 e0       ldi        r24, 0x03    ; 3
       8:        08 95       ret

    0000000a <LBB0_2>:
       a:        85 e0       ldi        r24, 0x05    ; 5
       c:        08 95       ret

This patch fixes that, the output is now:

    00000000 <foo>:
       0:        81 70       andi       r24, 0x01    ; 1
       2:        80 30       cpi        r24, 0x00    ; 0
       4:        01 f0       breq       .+0          ; 0x6 <foo+0x6>
       6:        83 e0       ldi        r24, 0x03    ; 3
       8:        08 95       ret
       a:        85 e0       ldi        r24, 0x05    ; 5
       c:        08 95       ret

Note that as you can see the breq operand is different. However it is
still the same after linking:

       4:        11 f0       breq       .+4

Differential Revision: https://reviews.llvm.org/D75124
This commit is contained in:
Ayke van Laethem 2020-02-25 17:15:34 +01:00
parent 350598f8a1
commit 8f4cb72386
9 changed files with 25 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/AVR/MCTargetDesc/AVRMCAsmInfo.cpp
View File

@ -21,6 +21,7 @@ AVRMCAsmInfo::AVRMCAsmInfo(const Triple &TT, const MCTargetOptions &Options) {
CalleeSaveStackSlotSize = 2;
CommentString = ";";
PrivateGlobalPrefix = ".L";
PrivateLabelPrefix = ".L";
UsesELFSectionDirectiveForBSS = true;
UseIntegratedAssembler = true;
SupportsDebugInformation = true;

8
test/CodeGen/AVR/branch-relaxation-long.ll
View File

@ -2,8 +2,8 @@
; CHECK-LABEL: relax_to_jmp:
; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: brne [[BB1:LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB2:LBB[0-9]+_[0-9]+]]
; CHECK: brne [[BB1:.LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: [[BB1]]:
; CHECK: nop
; CHECK: [[BB2]]:
@ -2069,10 +2069,10 @@ finished:
}
; CHECK-LABEL: relax_to_jmp_backwards:
; CHECK: [[BB1:LBB[0-9]+_[0-9]+]]
; CHECK: [[BB1:.LBB[0-9]+_[0-9]+]]
; CHECK: nop
; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: breq [[BB2:LBB[0-9]+_[0-9]+]]
; CHECK: breq [[BB2:.LBB[0-9]+_[0-9]+]]
; CHECK: jmp [[BB1]]
; CHECK: [[BB2]]:
define i8 @relax_to_jmp_backwards(i1 %a) {

10
test/CodeGen/AVR/branch-relaxation.ll
View File

@ -2,9 +2,9 @@
; CHECK-LABEL: relax_breq
; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: brne LBB0_1
; CHECK: rjmp LBB0_2
; LBB0_1:
; CHECK: brne .LBB0_1
; CHECK: rjmp .LBB0_2
; .LBB0_1:
define i8 @relax_breq(i1 %a) {
entry-block:
@ -68,10 +68,10 @@ finished:
; CHECK-LABEL: no_relax_breq
; CHECK: cpi r{{[0-9]+}}, 0
; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]]
; CHECK: breq [[END_BB:.LBB[0-9]+_[0-9]+]]
; CHECK: nop
; ...
; LBB0_1:
; .LBB0_1:
define i8 @no_relax_breq(i1 %a) {
entry-block:
br i1 %a, label %hello, label %finished

4
test/CodeGen/AVR/ctlz.ll
View File

@ -10,8 +10,8 @@ declare i8 @llvm.ctlz.i8(i8)
; CHECK-LABEL: count_leading_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0
; CHECK: brne LBB0_1
; CHECK: rjmp LBB0_2
; CHECK: brne .LBB0_1
; CHECK: rjmp .LBB0_2
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: lsr {{.*}}[[SCRATCH]]
; CHECK: or {{.*}}[[SCRATCH]], {{.*}}[[RESULT]]

2
test/CodeGen/AVR/cttz.ll
View File

@ -10,7 +10,7 @@ declare i8 @llvm.cttz.i8(i8)
; CHECK-LABEL: count_trailing_zeros:
; CHECK: cpi [[RESULT:r[0-9]+]], 0
; CHECK: breq [[END_BB:LBB[0-9]+_[0-9]+]]
; CHECK: breq [[END_BB:.LBB[0-9]+_[0-9]+]]
; CHECK: mov [[SCRATCH:r[0-9]+]], {{.*}}[[RESULT]]
; CHECK: dec {{.*}}[[SCRATCH]]
; CHECK: com {{.*}}[[RESULT]]

4
test/CodeGen/AVR/integration/blink.ll
View File

@ -89,7 +89,7 @@ entry:
br label %while.body
; CHECK-LABEL: LBB3_1
; CHECK-LABEL: .LBB3_1
while.body:
; CHECK: call turn_on
@ -98,6 +98,6 @@ while.body:
; CHECK-NEXT: call turn_off
call void @turn_off()
; CHECK-NEXT: rjmp LBB3_1
; CHECK-NEXT: rjmp .LBB3_1
br label %while.body
}

16
test/CodeGen/AVR/rot.ll
View File

@ -7,15 +7,15 @@ define i8 @rol8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
; CHECK-NEXT: cpi r22, 0
; CHECK-NEXT: breq LBB0_2
; CHECK-NEXT: breq .LBB0_2
; CHECK-NEXT: LBB0_1:
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: lsl r24
; CHECK-NEXT: adc r24, r1
; CHECK-NEXT: subi r22, 1
; CHECK-NEXT: brne LBB0_1
; CHECK-NEXT: brne .LBB0_1
; CHECK-NEXT:LBB0_2:
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8
@ -34,17 +34,17 @@ define i8 @ror8(i8 %val, i8 %amt) {
; CHECK: andi r22, 7
; CHECK-NEXT: cpi r22, 0
; CHECK-NEXT: breq LBB1_2
; CHECK-NEXT: breq .LBB1_2
; CHECK-NEXT: LBB1_1:
; CHECK-NEXT: .LBB1_1:
; CHECK-NEXT: lsr r24
; CHECK-NEXT: ldi r0, 0
; CHECK-NEXT: ror r0
; CHECK-NEXT: or r24, r0
; CHECK-NEXT: subi r22, 1
; CHECK-NEXT: brne LBB1_1
; CHECK-NEXT: brne .LBB1_1
; CHECK-NEXT:LBB1_2:
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: ret
%mod = urem i8 %amt, 8

2
test/CodeGen/AVR/smul-with-overflow.ll
View File

@ -22,7 +22,7 @@ entry-block:
; CHECK: asr {{.*}}[[LOW]]
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cp {{.*}}[[HIGH]], {{.*}}[[LOW]]
; CHECK: brne [[LABEL:LBB[_0-9]+]]
; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret

2
test/CodeGen/AVR/umul-with-overflow.ll
View File

@ -13,7 +13,7 @@ entry-block:
; CHECK: mov [[HIGH:r[0-9]+]], r1
; CHECK: ldi [[RET:r[0-9]+]], 1
; CHECK: cpi {{.*}}[[HIGH]], 0
; CHECK: brne [[LABEL:LBB[_0-9]+]]
; CHECK: brne [[LABEL:.LBB[_0-9]+]]
; CHECK: ldi {{.*}}[[RET]], 0
; CHECK: {{.*}}[[LABEL]]
; CHECK: ret