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Make ReplaceATOMIC_BINARY_64 a static function. Use a nested switch to reduce to only a single call to it thus allowing it to be inlined by the compiler.
llvm-svn: 162088
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@ -11202,9 +11202,9 @@ static void ReplaceATOMIC_LOAD(SDNode *Node,
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Results.push_back(Swap.getValue(1));
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Results.push_back(Swap.getValue(1));
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}
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}
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void X86TargetLowering::
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static void
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ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
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ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results,
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SelectionDAG &DAG, unsigned NewOp) const {
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SelectionDAG &DAG, unsigned NewOp) {
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DebugLoc dl = Node->getDebugLoc();
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DebugLoc dl = Node->getDebugLoc();
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assert (Node->getValueType(0) == MVT::i64 &&
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assert (Node->getValueType(0) == MVT::i64 &&
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"Only know how to expand i64 atomics");
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"Only know how to expand i64 atomics");
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@ -11325,26 +11325,40 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
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return;
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return;
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}
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}
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case ISD::ATOMIC_LOAD_ADD:
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case ISD::ATOMIC_LOAD_ADD:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG);
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return;
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case ISD::ATOMIC_LOAD_AND:
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case ISD::ATOMIC_LOAD_AND:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG);
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return;
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case ISD::ATOMIC_LOAD_NAND:
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case ISD::ATOMIC_LOAD_NAND:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG);
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return;
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case ISD::ATOMIC_LOAD_OR:
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case ISD::ATOMIC_LOAD_OR:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG);
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return;
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case ISD::ATOMIC_LOAD_SUB:
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case ISD::ATOMIC_LOAD_SUB:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG);
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return;
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case ISD::ATOMIC_LOAD_XOR:
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case ISD::ATOMIC_LOAD_XOR:
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG);
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case ISD::ATOMIC_SWAP: {
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return;
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unsigned Opc;
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case ISD::ATOMIC_SWAP:
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switch (N->getOpcode()) {
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ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG);
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default: llvm_unreachable("Unexpected opcode");
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case ISD::ATOMIC_LOAD_ADD:
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Opc = X86ISD::ATOMADD64_DAG;
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break;
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case ISD::ATOMIC_LOAD_AND:
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Opc = X86ISD::ATOMAND64_DAG;
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break;
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case ISD::ATOMIC_LOAD_NAND:
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Opc = X86ISD::ATOMNAND64_DAG;
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break;
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case ISD::ATOMIC_LOAD_OR:
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Opc = X86ISD::ATOMOR64_DAG;
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break;
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case ISD::ATOMIC_LOAD_SUB:
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Opc = X86ISD::ATOMSUB64_DAG;
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break;
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case ISD::ATOMIC_LOAD_XOR:
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Opc = X86ISD::ATOMXOR64_DAG;
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break;
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case ISD::ATOMIC_SWAP:
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Opc = X86ISD::ATOMSWAP64_DAG;
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break;
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}
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ReplaceATOMIC_BINARY_64(N, Results, DAG, Opc);
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return;
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return;
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}
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case ISD::ATOMIC_LOAD:
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case ISD::ATOMIC_LOAD:
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ReplaceATOMIC_LOAD(N, Results, DAG);
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ReplaceATOMIC_LOAD(N, Results, DAG);
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}
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}
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@ -864,9 +864,6 @@ namespace llvm {
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const;
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LLVMContext &Context) const;
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void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG, unsigned NewOp) const;
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/// Utility function to emit string processing sse4.2 instructions
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/// Utility function to emit string processing sse4.2 instructions
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/// that return in xmm0.
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/// that return in xmm0.
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/// This takes the instruction to expand, the associated machine basic
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/// This takes the instruction to expand, the associated machine basic
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