[PowerPC] Add some InstAlias definitions

Summary:
This patch add the InstAlias definitions for below instructions.

ADDI ADDIS ADDI8 ADDIS8
RLWINM8
ISEL ISEL8
OR OR_rec ORI ORI8 XORI8
CNTLZW8 CNTLZW8_rec
TEND TSR
RFEBB
NOR NOR_rec
MTCRF
SUBF SUBF_rec SUBFC SUBFC_rec
RLDICL_32_64
TW

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D77559

lib/Target/PowerPC/PPCInstr64Bit.td

@@ -924,6 +924,9 @@ def ISEL8   : AForm_4<31, 15,
 }  // hasSideEffects = 0
 }  // End FXU Operations.
 
+def : InstAlias<"li $rD, $imm", (ADDI8 g8rc:$rD, ZERO8, s16imm64:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS8 g8rc:$rD, ZERO8, s17imm64:$imm)>;
+
 def : InstAlias<"mr $rA, $rB", (OR8 g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 def : InstAlias<"mr. $rA, $rB", (OR8_rec g8rc:$rA, g8rc:$rB, g8rc:$rB)>;
 
@@ -941,6 +944,21 @@ def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, u5imm:$n, 0,
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM8 g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
 def : InstAlias<"rotlw. $rA, $rS, $rB", (RLWNM8_rec g8rc:$rA, g8rc:$rS, g8rc:$rB, 0, 31)>;
+def : InstAlias<"clrlwi $rA, $rS, $n", (RLWINM8 g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+def : InstAlias<"clrlwi. $rA, $rS, $n", (RLWINM8_rec g8rc:$rA, g8rc:$rS, 0, u5imm:$n, 31)>;
+
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL8 g8rc:$rT, g8rc_nox0:$rA, g8rc:$rB, CR0EQ)>;
+
+def : InstAlias<"nop", (ORI8 X0, X0, 0)>;
+def : InstAlias<"xnop", (XORI8 X0, X0, 0)>;
+
+def : InstAlias<"cntlzw $rA, $rS", (CNTLZW8 g8rc:$rA, g8rc:$rS)>;
+def : InstAlias<"cntlzw. $rA, $rS", (CNTLZW8_rec g8rc:$rA, g8rc:$rS)>;
 
 //===----------------------------------------------------------------------===//
 // Load/Store instructions.

lib/Target/PowerPC/PPCInstrHTM.td

@@ -169,3 +169,8 @@ def : Pat<(i64 (int_ppc_ttest)),
                    36, 28)>;
 
 } // [HasHTM]
+
+def : InstAlias<"tend.", (TEND 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tendall.", (TEND 1)>, Requires<[HasHTM]>;
+def : InstAlias<"tsuspend.", (TSR 0)>, Requires<[HasHTM]>;
+def : InstAlias<"tresume.", (TSR 1)>, Requires<[HasHTM]>;

lib/Target/PowerPC/PPCInstrInfo.td

@@ -1780,6 +1780,8 @@ def RFEBB : XLForm_S<19, 146, (outs), (ins u1imm:$imm), "rfebb $imm",
                      IIC_BrB, [(PPCrfebb (i32 imm:$imm))]>,
                      PPC970_DGroup_Single;
 
+def : InstAlias<"rfebb", (RFEBB 1)>;
+
 // DCB* instructions.
 def DCBA   : DCB_Form<758, 0, (outs), (ins memrr:$dst), "dcba $dst",
                       IIC_LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
@@ -2392,6 +2394,9 @@ let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
 }
 }
 
+def : InstAlias<"li $rD, $imm", (ADDI gprc:$rD, ZERO, s16imm:$imm)>;
+def : InstAlias<"lis $rD, $imm", (ADDIS gprc:$rD, ZERO, s17imm:$imm)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let Defs = [CR0] in {
 def ANDI_rec : DForm_4<28, (outs gprc:$dst), (ins gprc:$src1, u16imm:$src2),
@@ -2480,6 +2485,14 @@ defm SRAW : XForm_6rc<31, 792, (outs gprc:$rA), (ins gprc:$rS, gprc:$rB),
                       [(set i32:$rA, (PPCsra i32:$rS, i32:$rB))]>;
 }
 
+def : InstAlias<"mr $rA, $rB", (OR gprc:$rA, gprc:$rB, gprc:$rB)>;
+def : InstAlias<"mr. $rA, $rB", (OR_rec gprc:$rA, gprc:$rB, gprc:$rB)>;
+
+def : InstAlias<"not $rA, $rS", (NOR gprc:$rA, gprc:$rS, gprc:$rS)>;
+def : InstAlias<"not. $rA, $rS", (NOR_rec gprc:$rA, gprc:$rS, gprc:$rS)>;
+
+def : InstAlias<"nop", (ORI R0, R0, 0)>;
+
 let PPC970_Unit = 1 in {  // FXU Operations.
 let hasSideEffects = 0 in {
 defm SRAWI : XForm_10rc<31, 824, (outs gprc:$rA), (ins gprc:$rS, u5imm:$SH),
@@ -2847,6 +2860,8 @@ def MCRXRX : X_BF3<31, 576, (outs crrc:$BF), (ins),
                    "mcrxrx $BF", IIC_BrMCRX>, Requires<[IsISA3_0]>;
 } // hasSideEffects = 0
 
+def : InstAlias<"mtcr $rA", (MTCRF 255, gprc:$rA)>;
+
 let Predicates = [HasFPU] in {
 // Custom inserter instruction to perform FADD in round-to-zero mode.
 let Uses = [RM] in {
@@ -2992,6 +3007,11 @@ defm SUBFZE : XOForm_3rc<31, 200, 0, (outs gprc:$rT), (ins gprc:$rA),
 }
 }
 
+def : InstAlias<"sub $rA, $rB, $rC", (SUBF gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"sub. $rA, $rB, $rC", (SUBF_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc $rA, $rB, $rC", (SUBFC gprc:$rA, gprc:$rC, gprc:$rB)>;
+def : InstAlias<"subc. $rA, $rB, $rC", (SUBFC_rec gprc:$rA, gprc:$rC, gprc:$rB)>;
+
 // A-Form instructions.  Most of the instructions executed in the FPU are of
 // this type.
 //
@@ -4689,6 +4709,13 @@ def CLRLSLWI : PPCAsmPseudo<"clrlslwi $rA, $rS, $b, $n",
 def CLRLSLWI_rec : PPCAsmPseudo<"clrlslwi. $rA, $rS, $b, $n",
                              (ins gprc:$rA, gprc:$rS, u5imm:$b, u5imm:$n)>;
 
+def : InstAlias<"isellt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0LT)>;
+def : InstAlias<"iselgt $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0GT)>;
+def : InstAlias<"iseleq $rT, $rA, $rB",
+                (ISEL gprc:$rT, gprc_nor0:$rA, gprc:$rB, CR0EQ)>;
+
 def : InstAlias<"rotlwi $rA, $rS, $n", (RLWINM gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlwi. $rA, $rS, $n", (RLWINM_rec gprc:$rA, gprc:$rS, u5imm:$n, 0, 31)>;
 def : InstAlias<"rotlw $rA, $rS, $rB", (RLWNM gprc:$rA, gprc:$rS, gprc:$rB, 0, 31)>;
@@ -4737,6 +4764,8 @@ def CLRLSLDI_rec : PPCAsmPseudo<"clrlsldi. $rA, $rS, $b, $n",
 def SUBPCIS : PPCAsmPseudo<"subpcis $RT, $D", (ins g8rc:$RT, s16imm:$D)>;
 
 def : InstAlias<"rotldi $rA, $rS, $n", (RLDICL g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
+def : InstAlias<"rotldi $rA, $rS, $n",
+                (RLDICL_32_64 g8rc:$rA, gprc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotldi. $rA, $rS, $n", (RLDICL_rec g8rc:$rA, g8rc:$rS, u6imm:$n, 0)>;
 def : InstAlias<"rotld $rA, $rS, $rB", (RLDCL g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
 def : InstAlias<"rotld. $rA, $rS, $rB", (RLDCL_rec g8rc:$rA, g8rc:$rS, gprc:$rB, 0)>;
@@ -4935,6 +4964,8 @@ def : InstAlias<"cmp $bf, 1, $rA, $rB", (CMPD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 def : InstAlias<"cmpli $bf, 1, $rA, $imm", (CMPLDI crrc:$bf, g8rc:$rA, u16imm64:$imm)>;
 def : InstAlias<"cmpl $bf, 1, $rA, $rB", (CMPLD crrc:$bf, g8rc:$rA, g8rc:$rB)>;
 
+def : InstAlias<"trap", (TW 31, R0, R0)>;
+
 multiclass TrapExtendedMnemonic<string name, int to> {
   def : InstAlias<"td"#name#"i $rA, $imm", (TDI to, g8rc:$rA, s16imm:$imm)>;
   def : InstAlias<"td"#name#" $rA, $rB", (TD to, g8rc:$rA, g8rc:$rB)>;

test/CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll

@@ -3,7 +3,7 @@
 ; The first argument of subfc must not be the same as any other register.
 
 ; CHECK: APP
-; CHECK: subfc [[REG:[0-9]+]],
+; CHECK: subc [[REG:[0-9]+]],
 ; CHECK-NOT: [[REG]]
 ; CHECK: NO_APP
 ; PR1357

test/CodeGen/PowerPC/2009-09-18-carrybit.ll

@@ -6,9 +6,9 @@ target triple = "powerpc-unknown-linux-gnu.6"
 define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
 entry:
 ; CHECK-LABEL: foo:
-; CHECK: subfc
+; CHECK: subc
 ; CHECK: subfe
-; CHECK: subfc
+; CHECK: subc
 ; CHECK: subfe
   %tmp0 = add i64 %r.0.ph, -1                           ; <i64> [#uses=1]
   br label %bb40

test/CodeGen/PowerPC/2010-02-12-saveCR.ll

@@ -7,7 +7,7 @@ define void @foo() nounwind {
 entry:
 ; Note that part of what is being checked here is proper register reuse.
 ; CHECK: mfcr [[T1:[0-9]+]]
-; CHECK-DAG: subf 0, 0, 1
+; CHECK-DAG: sub 0, 1, 0
 ; CHECK-DAG: ori [[T2:[0-9]+]], [[T2]], 34492
 ; CHECK-DAG: stwx [[T1]], 1, [[T2]]
 ; CHECK-DAG: addi 3, 1, 28

test/CodeGen/PowerPC/CompareEliminationSpillIssue.ll

@@ -32,7 +32,7 @@ entry:
   %conv1 = zext i1 %cmp to i32
   ret i32 %conv1
 ; CHECK-LABEL: test
-; CHECK: subf r3,
+; CHECK: sub r3,
 ; CHECK: extsw r3,
 ; CHECK: bl call
 ; CHECK: sub r3,

test/CodeGen/PowerPC/atomics-regression.ll

@@ -2734,7 +2734,7 @@ define i8 @test160(i8* %ptr, i8 %val) {
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB160_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB160_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2750,7 +2750,7 @@ define i8 @test161(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB161_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB161_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2766,7 +2766,7 @@ define i8 @test162(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB162_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB162_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2782,7 +2782,7 @@ define i8 @test163(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB163_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB163_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2799,7 +2799,7 @@ define i8 @test164(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB164_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB164_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2815,7 +2815,7 @@ define i16 @test165(i16* %ptr, i16 %val) {
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB165_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB165_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2831,7 +2831,7 @@ define i16 @test166(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB166_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB166_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2847,7 +2847,7 @@ define i16 @test167(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB167_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB167_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2863,7 +2863,7 @@ define i16 @test168(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB168_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB168_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2880,7 +2880,7 @@ define i16 @test169(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB169_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB169_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2896,7 +2896,7 @@ define i32 @test170(i32* %ptr, i32 %val) {
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB170_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB170_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2912,7 +2912,7 @@ define i32 @test171(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB171_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB171_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2928,7 +2928,7 @@ define i32 @test172(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB172_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB172_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2944,7 +2944,7 @@ define i32 @test173(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB173_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB173_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -2961,7 +2961,7 @@ define i32 @test174(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB174_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB174_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6458,7 +6458,7 @@ define i8 @test380(i8* %ptr, i8 %val) {
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB380_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB380_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6474,7 +6474,7 @@ define i8 @test381(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB381_1:
 ; PPC64LE-NEXT:    lbarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB381_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6490,7 +6490,7 @@ define i8 @test382(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB382_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB382_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6506,7 +6506,7 @@ define i8 @test383(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB383_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB383_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6523,7 +6523,7 @@ define i8 @test384(i8* %ptr, i8 %val) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB384_1:
 ; PPC64LE-NEXT:    lbarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stbcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB384_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6539,7 +6539,7 @@ define i16 @test385(i16* %ptr, i16 %val) {
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB385_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB385_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6555,7 +6555,7 @@ define i16 @test386(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB386_1:
 ; PPC64LE-NEXT:    lharx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB386_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6571,7 +6571,7 @@ define i16 @test387(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB387_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB387_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6587,7 +6587,7 @@ define i16 @test388(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB388_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB388_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6604,7 +6604,7 @@ define i16 @test389(i16* %ptr, i16 %val) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB389_1:
 ; PPC64LE-NEXT:    lharx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    sthcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB389_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6620,7 +6620,7 @@ define i32 @test390(i32* %ptr, i32 %val) {
 ; PPC64LE:       # %bb.0:
 ; PPC64LE-NEXT:  .LBB390_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB390_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6636,7 +6636,7 @@ define i32 @test391(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    mr 5, 3
 ; PPC64LE-NEXT:  .LBB391_1:
 ; PPC64LE-NEXT:    lwarx 3, 0, 5
-; PPC64LE-NEXT:    subf 6, 4, 3
+; PPC64LE-NEXT:    sub 6, 3, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 5
 ; PPC64LE-NEXT:    bne 0, .LBB391_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6652,7 +6652,7 @@ define i32 @test392(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB392_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB392_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6668,7 +6668,7 @@ define i32 @test393(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    lwsync
 ; PPC64LE-NEXT:  .LBB393_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB393_1
 ; PPC64LE-NEXT:  # %bb.2:
@@ -6685,7 +6685,7 @@ define i32 @test394(i32* %ptr, i32 %val) {
 ; PPC64LE-NEXT:    sync
 ; PPC64LE-NEXT:  .LBB394_1:
 ; PPC64LE-NEXT:    lwarx 5, 0, 3
-; PPC64LE-NEXT:    subf 6, 4, 5
+; PPC64LE-NEXT:    sub 6, 5, 4
 ; PPC64LE-NEXT:    stwcx. 6, 0, 3
 ; PPC64LE-NEXT:    bne 0, .LBB394_1
 ; PPC64LE-NEXT:  # %bb.2:

test/CodeGen/PowerPC/crbits.ll

@@ -24,7 +24,7 @@ entry:
 ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK: blr
 }
@@ -134,7 +134,7 @@ entry:
 
 ; CHECK-LABEL: @test7
 ; CHECK: andi. {{[0-9]+}}, 3, 1
-; CHECK: isel 3, 4, 5, 1
+; CHECK: iselgt 3, 4, 5
 ; CHECK: blr
 }
 
@@ -148,7 +148,7 @@ entry:
 ; CHECK-DAG: cmpwi 3, 5
 ; CHECK-DAG: li [[REG1:[0-9]+]], 8
 ; CHECK-DAG: li [[REG2:[0-9]+]], 7
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK: iseleq 3, [[REG2]], [[REG1]]
 ; CHECK-NOT: rldicl
 ; CHECK: blr
 }

test/CodeGen/PowerPC/eqv-andc-orc-nor.ll

@@ -5,7 +5,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep orc | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -mcpu=g5 | \
-; RUN:   grep nor | count 3
+; RUN:   grep nor | count 2
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | \
 ; RUN:   grep nand | count 1
 

test/CodeGen/PowerPC/expand-contiguous-isel.ll

@@ -132,8 +132,8 @@ _ZNK4llvm9StringRef6substrEmm.exit:
 
 ; CHECK-LABEL: @_Z3fn1N4llvm9StringRefE
 ; Unecessary ISEL (all the registers are the same) is always removed
-; CHECK-GEN-ISEL-TRUE-NOT: isel [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
+; CHECK-GEN-ISEL-TRUE-NOT: iseleq [[SAME:r[0-9]+]], [[SAME]], [[SAME]]
-; CHECK-GEN-ISEL-TRUE: isel [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
+; CHECK-GEN-ISEL-TRUE: iseleq [[SAME:r[0-9]+]], {{r[0-9]+}}, [[SAME]]
 ; CHECK: bc 12, eq, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NEXT: [[TRUE]]

test/CodeGen/PowerPC/expand-isel.ll

@@ -163,7 +163,7 @@ entry:
 ; CHECK-NEXT:  [[SUCCESSOR]]
 ; CHECK-NEXT: add r4, r4, r6
 ; CHECK-NEXT: add r3, r3, r4
-; CHECK-NEXT: subf r3, r5, r3
+; CHECK-NEXT: sub r3, r3, r5
 ; CHECK-NEXT: extsw r3, r3
 ; CHECK-NEXT: blr
 }

test/CodeGen/PowerPC/f128-compare.ll

@@ -15,7 +15,7 @@ entry:
   ret i32 %conv
 ; CHECK-LABEL: greater_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, gt
+; CHECK: iselgt r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: blr
 }
 
@@ -29,7 +29,7 @@ entry:
   ret i32 %conv
 ; CHECK-LABEL: less_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, lt
+; CHECK: isellt r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: blr
 }
 
@@ -73,7 +73,7 @@ entry:
   ret i32 %conv
 ; CHECK-LABEL: equal_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, eq
+; CHECK: iseleq r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK: blr
 }
 
@@ -88,7 +88,7 @@ entry:
   ret i32 %lnot.ext
 ; CHECK-LABEL: not_greater_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, gt
+; CHECK: iselgt r{{[0-9]+}}, 0, r{{[0-9]+}}
 ; CHECK: blr
 }
 
@@ -103,7 +103,7 @@ entry:
   ret i32 %lnot.ext
 ; CHECK-LABEL: not_less_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, lt
+; CHECK: isellt r{{[0-9]+}}, 0, r{{[0-9]+}}
 ; CHECK: blr
 }
 
@@ -149,7 +149,7 @@ entry:
   ret i32 %conv
 ; CHECK-LABEL: not_equal_qp
 ; CHECK: xscmpuqp
-; CHECK: isel r{{[0-9]+}}, 0, r{{[0-9]+}}, eq
+; CHECK: iseleq r{{[0-9]+}}, 0, r{{[0-9]+}}
 ; CHECK: blr
 }
 

test/CodeGen/PowerPC/fast-isel-binary.ll

@@ -91,7 +91,7 @@ entry:
 ; ELF64: sub_i8
   %a.addr = alloca i8, align 4
   %0 = sub i8 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i8 %0, i8* %a.addr, align 4
   ret void
 }
@@ -111,7 +111,7 @@ entry:
 ; ELF64: sub_i16
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, %b
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }
@@ -131,7 +131,7 @@ entry:
 ; ELF64: sub_i16_imm
   %a.addr = alloca i16, align 4
   %0 = sub i16 %a, -32768;
-; ELF64: subf
+; ELF64: sub
   store i16 %0, i16* %a.addr, align 4
   ret void
 }

test/CodeGen/PowerPC/fold-remove-li.ll

@@ -13,7 +13,7 @@ define dso_local signext i32 @redunLoadImm(%0* %arg) {
 ; CHECK-LABEL: redunLoadImm:
 ; verify that the load immediate has been folded into the isel and deleted
 ; CHECK-NOT:   li r[[REG1:[0-9]+]], 0
-; CHECK:       isel r[[REG2:[0-9]+]], 0, r[[REG3:[0-9]+]], eq
+; CHECK:       iseleq r[[REG2:[0-9]+]], 0, r[[REG3:[0-9]+]]
 
 bb:
   %tmp = icmp eq %0* %arg, null

test/CodeGen/PowerPC/fold-zero.ll

@@ -10,7 +10,7 @@ define i32 @test1(i1 %a, i32 %c) nounwind  {
 
 ; CHECK-LABEL: @test1
 ; CHECK-NOT: li {{[0-9]+}}, 0
-; CHECK: isel 3, 0,
+; CHECK: iseleq 3, 0,
 ; CHECK: blr
 ; CHECK-NO-ISEL-LABEL: @test1
 ; CHECK-NO-ISEL: li 3, 0
@@ -27,14 +27,14 @@ define i32 @test2(i1 %a, i32 %c) nounwind  {
 
 ; CHECK-CRB-LABEL: @test2
 ; CHECK-CRB-NOT: li {{[0-9]+}}, 0
-; CHECK-CRB: isel 3, 0,
+; CHECK-CRB: iselgt 3, 0,
 ; CHECK-CRB: blr
 ; CHECK-NO-ISEL-LABEL: @test2
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 4, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 

test/CodeGen/PowerPC/funnel-shift.ll

@@ -23,7 +23,7 @@ define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
 ; CHECK-NEXT:    slw 5, 3, 5
 ; CHECK-NEXT:    srw 4, 4, 6
 ; CHECK-NEXT:    or 4, 5, 4
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
   ret i32 %f
@@ -49,7 +49,7 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
 ; CHECK-NEXT:    sld 5, 3, 5
 ; CHECK-NEXT:    srd 4, 4, 6
 ; CHECK-NEXT:    or 4, 5, 4
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
   ret i37 %f
@@ -129,7 +129,7 @@ define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
 ; CHECK-NEXT:    srw 5, 4, 5
 ; CHECK-NEXT:    slw 3, 3, 6
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    isel 3, 4, 3, 2
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
   ret i32 %f
@@ -155,7 +155,7 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
 ; CHECK-NEXT:    srd 5, 6, 5
 ; CHECK-NEXT:    sld 3, 3, 7
 ; CHECK-NEXT:    or 3, 3, 5
-; CHECK-NEXT:    isel 3, 4, 3, 2
+; CHECK-NEXT:    iseleq 3, 4, 3
 ; CHECK-NEXT:    blr
   %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
   ret i37 %f

test/CodeGen/PowerPC/handle-f16-storage-type.ll

@@ -1267,7 +1267,7 @@ define half @PR40273(half) #0 {
 ; SOFT-NEXT:    nop
 ; SOFT-NEXT:    cmplwi r3, 0
 ; SOFT-NEXT:    lis r3, 16256
-; SOFT-NEXT:    isel r3, 0, r3, eq
+; SOFT-NEXT:    iseleq r3, 0, r3
 ; SOFT-NEXT:    bl __gnu_f2h_ieee
 ; SOFT-NEXT:    nop
 ; SOFT-NEXT:    addi r1, r1, 32

test/CodeGen/PowerPC/htm.ll

@@ -22,7 +22,7 @@ entry:
   %0 = tail call i32 @llvm.ppc.tend(i32 0)
   ret i32 %0
 ; CHECK-LABEL: @test2
-; CHECK: tend. 0
+; CHECK: tend.
 ; CHECK: mfocrf  {{[0-9]+}}, 128
 }
 
@@ -60,9 +60,9 @@ entry:
   %3 = tail call i64 @llvm.ppc.ttest()
   ret void
 ; CHECK-LABEL: @test4
-; CHECK: tend. 1
+; CHECK: tendall.
-; CHECK: tsr.  1
+; CHECK: tresume.
-; CHECK: tsr.  0
+; CHECK: tsuspend.
 ; CHECK: tabortwci. 0, {{[0-9]+}}, 0
 }
 
@@ -138,7 +138,7 @@ entry:
 ; CHECK: tcheck [[REG1:[0-9]+]] 
 ; CHECK: treclaim. [[REG2:[0-9]+]] 
 ; CHECK: trechkpt. 
-; CHECK: tsr.  1
+; CHECK: tresume.
 }
 
 declare i32 @llvm.ppc.tcheck()

test/CodeGen/PowerPC/i1-ext-fold.ll

@@ -16,7 +16,7 @@ entry:
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 16
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK: isellt 3, [[REG2]], [[REG1]]
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bclr 12, 0, 0
@@ -38,7 +38,7 @@ entry:
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 5
 ; CHECK-DAG: li [[REG2:[0-9]+]], 21
-; CHECK: isel 3, [[REG2]], [[REG1]],
+; CHECK: isellt 3, [[REG2]], [[REG1]]
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bclr 12, 0, 0
@@ -58,14 +58,14 @@ entry:
 ; CHECK-NO-ISEL-LABEL: @foo3
 ; CHECK-DAG: cmpw
 ; CHECK-DAG: li [[REG1:[0-9]+]], 16
-; CHECK: isel 3, 0, [[REG1]],
+; CHECK: iselgt 3, 0, [[REG1]]
 ; CHECK: blr
 
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 3, 5, 0
 ; CHECK-NO-ISEL-NEXT: blr
 ; CHECK-NO-ISEL-NEXT: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 3, 0, 0
+; CHECK-NO-ISEL-NEXT: li 3, 0
 ; CHECK-NO-ISEL-NEXT: blr
 }
 

test/CodeGen/PowerPC/i64_fp_round.ll

@@ -18,7 +18,7 @@ entry:
 ; CHECK: sradi [[REG1:[0-9]+]], 3, 53
 ; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
 ; CHECK: cmpldi [[REG2]], 1
-; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
+; CHECK: iselgt [[REG3:[0-9]+]], {{[0-9]+}}, 3
 ; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]

test/CodeGen/PowerPC/ifcvt.ll

@@ -22,8 +22,8 @@ cond.false:                                       ; preds = %sw.epilog
 ; CHECK-LABEL: @test
 ; CHECK-NO-ISEL-LABEL: @test
 ; CHECK: add [[REG:[0-9]+]], 
-; CHECK: subf [[REG2:[0-9]+]],
+; CHECK: sub [[REG2:[0-9]+]],
-; CHECK: isel {{[0-9]+}}, [[REG]], [[REG2]],
+; CHECK: iselgt {{[0-9]+}}, [[REG]], [[REG2]]
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]

test/CodeGen/PowerPC/inc-of-add.ll

@@ -406,13 +406,13 @@ define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
+; PPC32-NEXT:    not 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
+; PPC32-NEXT:    not 3, 3
-; PPC32-NEXT:    subfc 4, 4, 8
+; PPC32-NEXT:    subc 4, 8, 4
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
+; PPC32-NEXT:    not 5, 5
-; PPC32-NEXT:    subfc 6, 6, 10
+; PPC32-NEXT:    subc 6, 10, 6
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
 ;

test/CodeGen/PowerPC/loop-instr-form-prepare.ll

@@ -513,7 +513,7 @@ define i64 @test_ds_cross_basic_blocks(i8* %0, i32 signext %1) {
 ; CHECK-NEXT:    rlwinm r26, r27, 0, 0, 30
 ; CHECK-NEXT:    srwi r27, r27, 1
 ; CHECK-NEXT:    add r27, r27, r26
-; CHECK-NEXT:    subf r0, r27, r0
+; CHECK-NEXT:    sub r0, r0, r27
 ; CHECK-NEXT:    cmplwi r0, 1
 ; CHECK-NEXT:    beq cr0, .LBB6_2
 ; CHECK-NEXT:  # %bb.5: #

test/CodeGen/PowerPC/machine-pre.ll

@@ -96,7 +96,7 @@ define dso_local signext i32 @foo(i32 signext %x, i32 signext %y) nounwind {
 ; CHECK-P9-NEXT:    add r3, r3, r4
 ; CHECK-P9-NEXT:    slwi r4, r3, 1
 ; CHECK-P9-NEXT:    add r3, r3, r4
-; CHECK-P9-NEXT:    subf r3, r3, r28
+; CHECK-P9-NEXT:    sub r3, r28, r3
 ; CHECK-P9-NEXT:    cmplwi r3, 1
 ; CHECK-P9-NEXT:    beq cr0, .LBB1_1
 ; CHECK-P9-NEXT:  # %bb.5: # %while.cond

test/CodeGen/PowerPC/memcmp.ll

@@ -12,7 +12,7 @@ define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture rea
 ; CHECK-NEXT:    subfe 3, 3, 3
 ; CHECK-NEXT:    neg 4, 5
 ; CHECK-NEXT:    neg 3, 3
-; CHECK-NEXT:    subf 3, 3, 4
+; CHECK-NEXT:    sub 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
@@ -30,7 +30,7 @@ define signext i32 @memcmp4(i32* nocapture readonly %buffer1, i32* nocapture rea
 ; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    rldicl 4, 5, 1, 63
 ; CHECK-NEXT:    rldicl 3, 3, 1, 63
-; CHECK-NEXT:    subf 3, 3, 4
+; CHECK-NEXT:    sub 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
@@ -44,7 +44,7 @@ define signext i32 @memcmp2(i32* nocapture readonly %buffer1, i32* nocapture rea
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lhbrx 3, 0, 3
 ; CHECK-NEXT:    lhbrx 4, 0, 4
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*
@@ -58,7 +58,7 @@ define signext i32 @memcmp1(i32* nocapture readonly %buffer1, i32* nocapture rea
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lbz 3, 0(3)
 ; CHECK-NEXT:    lbz 4, 0(4)
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %t0 = bitcast i32* %buffer1 to i8*

test/CodeGen/PowerPC/mul-const.ll

@@ -25,7 +25,7 @@ define i32 @test3(i32 %a) {
 ; CHECK-LABEL: test3:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
-; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
+; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3
 
 ; negtive constant
 
@@ -56,7 +56,7 @@ define i32 @test6(i32 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 4
-; CHECK-NEXT: subf r[[REG2:[0-9]+]], r[[REG1]], r3
+; CHECK-NEXT: sub r[[REG2:[0-9]+]], r3, r[[REG1]]
 ; CHECK-NOT: neg
 
 ; boundary case
@@ -76,4 +76,4 @@ define i32 @test8(i32 %a) {
 ; CHECK-LABEL: test8:
 ; CHECK-NOT: mul
 ; CHECK: slwi r[[REG1:[0-9]+]], r3, 31
-; CHECK-NEXT: subf r[[REG2:[0-9]+]], r3, r[[REG1]]
+; CHECK-NEXT: sub r[[REG2:[0-9]+]], r[[REG1]], r3

test/CodeGen/PowerPC/noPermuteFormasking.ll

@@ -46,7 +46,7 @@ define signext i32 @andis_bot(i32 signext %a, i32 signext %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andis. 5, 3, 1
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    isel 4, 4, 5, 2
+; CHECK-NEXT:    iseleq 4, 4, 5
 ; CHECK-NEXT:    mullw 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
@@ -64,7 +64,7 @@ define signext i32 @andis_mid(i32 signext %a, i32 signext %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andis. 5, 3, 252
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    isel 4, 4, 5, 2
+; CHECK-NEXT:    iseleq 4, 4, 5
 ; CHECK-NEXT:    mullw 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
@@ -82,7 +82,7 @@ define signext i32 @andis_top(i32 signext %a, i32 signext %b) {
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    andis. 5, 3, 64512
 ; CHECK-NEXT:    li 5, 1
-; CHECK-NEXT:    isel 4, 4, 5, 2
+; CHECK-NEXT:    iseleq 4, 4, 5
 ; CHECK-NEXT:    mullw 3, 4, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr

test/CodeGen/PowerPC/optcmp.ll

@@ -9,8 +9,8 @@ define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 ; CHECK-LABEL: foo:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    cmpw 3, 4
-; CHECK-NEXT:    isel 6, 3, 4, 1
+; CHECK-NEXT:    iselgt 6, 3, 4
-; CHECK-NEXT:    subf 4, 4, 3
+; CHECK-NEXT:    sub 4, 3, 4
 ; CHECK-NEXT:    extsw 3, 6
 ; CHECK-NEXT:    stw 4, 0(5)
 ; CHECK-NEXT:    blr
@@ -25,7 +25,7 @@ define signext i32 @foo(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 ; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %entry
 ; CHECK-NO-ISEL-NEXT:    addi 6, 3, 0
 ; CHECK-NO-ISEL-NEXT:  .LBB0_3: # %entry
-; CHECK-NO-ISEL-NEXT:    subf 4, 4, 3
+; CHECK-NO-ISEL-NEXT:    sub 4, 3, 4
 ; CHECK-NO-ISEL-NEXT:    extsw 3, 6
 ; CHECK-NO-ISEL-NEXT:    stw 4, 0(5)
 ; CHECK-NO-ISEL-NEXT:    blr
@@ -45,7 +45,7 @@ define signext i32 @foo2(i32 signext %a, i32 signext %b, i32* nocapture %c) #0 {
 ; CHECK-NEXT:    li 3, 1
 ; CHECK-NEXT:    cmpwi 4, 0
 ; CHECK-NEXT:    stw 4, 0(5)
-; CHECK-NEXT:    isel 3, 3, 6, 1
+; CHECK-NEXT:    iselgt 3, 3, 6
 ; CHECK-NEXT:    blr
 ;
 ; CHECK-NO-ISEL-LABEL: foo2:
@@ -71,7 +71,7 @@ define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: fool:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
@@ -97,7 +97,7 @@ define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foolb:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 3, 4
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
@@ -123,7 +123,7 @@ define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foolc:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 4, 3
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
@@ -149,7 +149,7 @@ define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foold:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 4, 3
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
@@ -175,7 +175,7 @@ define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
 ; CHECK-LABEL: foold2:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    sub. 6, 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;
@@ -309,7 +309,7 @@ define signext i64 @fooct(i64 signext %a, i64 signext %b, i64* nocapture %c) #0
 ; CHECK-NEXT:    and 6, 6, 7
 ; CHECK-NEXT:    mulld 6, 6, 9
 ; CHECK-NEXT:    rldicl. 6, 6, 8, 56
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    std 6, 0(5)
 ; CHECK-NEXT:    blr
 ;

test/CodeGen/PowerPC/optimize-andiso.ll

@@ -13,7 +13,7 @@ define float @floatundisf(i64 %a) {
 ; CHECK-NEXT:    li r5, 2
 ; CHECK-NEXT:    andis. r4, r3, 1024
 ; CHECK-NEXT:    li r4, 3
-; CHECK-NEXT:    isel r4, r5, r4, eq
+; CHECK-NEXT:    iseleq r4, r5, r4
 ; CHECK-NEXT:    srd r3, r3, r4
 ; CHECK-NEXT:    clrlwi r3, r3, 9
 ; CHECK-NEXT:    mtfprd f0, r3

test/CodeGen/PowerPC/pcrel-call-linkage-leaf.ll

@@ -102,19 +102,19 @@ define dso_local signext i32 @X2IsCallerSaved(i32 signext %a, i32 signext %b, i3
 ; CHECK-ALL:       # %bb.0: # %entry
 ; CHECK-S-NEXT:    std r29, -24(r1) # 8-byte Folded Spill
 ; CHECK-S-NEXT:    add r11, r4, r3
-; CHECK-S-NEXT:    subf r29, r9, r8
+; CHECK-S-NEXT:    sub r29, r8, r9
 ; CHECK-S-NEXT:    add r9, r10, r9
-; CHECK-S-NEXT:    subf r10, r3, r10
+; CHECK-S-NEXT:    sub r10, r10, r3
 ; CHECK-S-NEXT:    mullw r3, r4, r3
 ; CHECK-S-NEXT:    mullw r3, r3, r11
 ; CHECK-S-NEXT:    mullw r3, r3, r5
-; CHECK-S-NEXT:    subf r12, r5, r4
+; CHECK-S-NEXT:    sub r12, r4, r5
 ; CHECK-S-NEXT:    mullw r3, r3, r6
 ; CHECK-S-NEXT:    add r0, r6, r5
 ; CHECK-S-NEXT:    mullw r3, r3, r12
 ; CHECK-S-NEXT:    mullw r3, r3, r0
 ; CHECK-S-NEXT:    mullw r3, r3, r7
-; CHECK-S-NEXT:    subf r2, r7, r6
+; CHECK-S-NEXT:    sub r2, r6, r7
 ; CHECK-S-NEXT:    mullw r3, r3, r8
 ; CHECK-S-NEXT:    std r30, -16(r1) # 8-byte Folded Spill
 ; CHECK-S-NEXT:    add r30, r8, r7

test/CodeGen/PowerPC/popcnt-zext.ll

@@ -15,7 +15,7 @@ define i16 @zpop_i8_i16(i8 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -51,7 +51,7 @@ define i16 @popz_i8_i16(i8 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -87,7 +87,7 @@ define i32 @zpop_i8_i32(i8 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -123,7 +123,7 @@ define i32 @popz_i8_32(i8 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 85
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -159,7 +159,7 @@ define i32 @zpop_i16_i32(i16 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -195,7 +195,7 @@ define i32 @popz_i16_32(i16 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -271,7 +271,7 @@ define i64 @popz_i32_i64(i32 %x) {
 ; SLOW-NEXT:    andi. 5, 5, 21845
 ; SLOW-NEXT:    or 5, 5, 6
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 5, 3
+; SLOW-NEXT:    sub 3, 3, 5
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4
@@ -308,7 +308,7 @@ define i64 @popa_i16_i64(i16 %x) {
 ; SLOW-NEXT:    rotlwi 3, 3, 31
 ; SLOW-NEXT:    andi. 3, 3, 21845
 ; SLOW-NEXT:    lis 4, 13107
-; SLOW-NEXT:    subf 3, 3, 5
+; SLOW-NEXT:    sub 3, 5, 3
 ; SLOW-NEXT:    ori 4, 4, 13107
 ; SLOW-NEXT:    rotlwi 5, 3, 30
 ; SLOW-NEXT:    and 3, 3, 4

test/CodeGen/PowerPC/ppc-crbits-onoff.ll

@@ -17,12 +17,12 @@ entry:
 ; CHECK-DAG: cmplwi 3, 0
 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
 ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
-; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
+; CHECK: iseleq [[REG4:[0-9]+]], 0, [[REG2]]
 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 4, 5, 0
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
+; CHECK-NO-ISEL-NEXT: li 4, 0
 ; CHECK: and 3, [[REG4]], [[REG3]]
 ; CHECK: blr
 }

test/CodeGen/PowerPC/ppc64-P9-mod.ll

@@ -187,14 +187,14 @@ entry:
 ; CHECK-NOT: modsw
 ; CHECK: slwi
 ; CHECK-NOT: modsw
-; CHECK: subf
+; CHECK: sub
 ; CHECK-NOT: modsw
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: modulo_const32_sw
 ; CHECK-PWR8: srawi
 ; CHECK-PWR8: addze
 ; CHECK-PWR8: slwi
-; CHECK-PWR8: subf
+; CHECK-PWR8: sub
 ; CHECK-PWR8: blr
 }
 

test/CodeGen/PowerPC/ppc64-P9-vabsd.ll

@@ -395,13 +395,13 @@ entry:
   ret <16 x i8> %vecins123
 ; CHECK-LABEL: sub_absv_8_ext
 ; CHECK-NOT: vabsdub
-; CHECK: subf
+; CHECK: sub
 ; CHECK-NOT: vabsdub
 ; CHECK: xor
 ; CHECK-NOT: vabsdub
 ; CHECK: blr
 ; CHECK-PWR8-LABEL: sub_absv_8_ext
-; CHECK-PWR8: subf
+; CHECK-PWR8: sub
 ; CHECK-PWR8: xor
 ; CHECK-PWR8: blr
 }

test/CodeGen/PowerPC/pr44183.ll

@@ -16,7 +16,7 @@ define void @_ZN1m1nEv(%struct.m.2.5.8.11* %this) local_unnamed_addr nounwind al
 ; CHECK-NEXT:    lwz r5, 36(r30)
 ; CHECK-NEXT:    rldicl r4, r4, 60, 4
 ; CHECK-NEXT:    rlwinm r3, r4, 31, 0, 0
-; CHECK-NEXT:    rlwinm r4, r5, 0, 31, 31
+; CHECK-NEXT:    clrlwi r4, r5, 31
 ; CHECK-NEXT:    or r4, r4, r3
 ; CHECK-NEXT:    bl _ZN1llsE1d
 ; CHECK-NEXT:    nop

test/CodeGen/PowerPC/remove-redundant-load-imm.ll

@@ -18,7 +18,7 @@ define void @redundancy_on_ppc_only(i1 %arg7) nounwind {
 ; PPC64LE-NEXT:    stdu 1, -32(1)
 ; PPC64LE-NEXT:    li 3, 1
 ; PPC64LE-NEXT:    li 4, 0
-; PPC64LE-NEXT:    isel 3, 3, 4, 1
+; PPC64LE-NEXT:    iselgt 3, 3, 4
 ; PPC64LE-NEXT:    bl barney.88
 ; PPC64LE-NEXT:    nop
 ; PPC64LE-NEXT:    addi 1, 1, 32

test/CodeGen/PowerPC/sat-add.ll

@@ -12,7 +12,7 @@ define i8 @unsigned_sat_constant_i8_using_min(i8 %x) {
 ; CHECK-NEXT:    clrlwi 5, 3, 24
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmplwi 5, 213
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i8 %x, -43
@@ -28,7 +28,7 @@ define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    andi. 4, 3, 256
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i8 %x, 42
   %c = icmp ugt i8 %x, %a
@@ -43,7 +43,7 @@ define i8 @unsigned_sat_constant_i8_using_cmp_notval(i8 %x) {
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    cmplwi 5, 213
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    blr
   %a = add i8 %x, 42
   %c = icmp ugt i8 %x, -43
@@ -57,7 +57,7 @@ define i16 @unsigned_sat_constant_i16_using_min(i16 %x) {
 ; CHECK-NEXT:    clrlwi 5, 3, 16
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmplwi 5, 65493
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i16 %x, -43
@@ -73,7 +73,7 @@ define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    andis. 4, 3, 1
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i16 %x, 42
   %c = icmp ugt i16 %x, %a
@@ -88,7 +88,7 @@ define i16 @unsigned_sat_constant_i16_using_cmp_notval(i16 %x) {
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    cmplwi 5, 65493
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    blr
   %a = add i16 %x, 42
   %c = icmp ugt i16 %x, -43
@@ -101,7 +101,7 @@ define i32 @unsigned_sat_constant_i32_using_min(i32 %x) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmplw 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i32 %x, -43
@@ -116,7 +116,7 @@ define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    cmplw 5, 3
-; CHECK-NEXT:    isel 3, 4, 5, 0
+; CHECK-NEXT:    isellt 3, 4, 5
 ; CHECK-NEXT:    blr
   %a = add i32 %x, 42
   %c = icmp ugt i32 %x, %a
@@ -131,7 +131,7 @@ define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, -1
-; CHECK-NEXT:    isel 3, 3, 5, 1
+; CHECK-NEXT:    iselgt 3, 3, 5
 ; CHECK-NEXT:    blr
   %a = add i32 %x, 42
   %c = icmp ugt i32 %x, -43
@@ -144,7 +144,7 @@ define i64 @unsigned_sat_constant_i64_using_min(i64 %x) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li 4, -43
 ; CHECK-NEXT:    cmpld 3, 4
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    addi 3, 3, 42
 ; CHECK-NEXT:    blr
   %c = icmp ult i64 %x, -43
@@ -159,7 +159,7 @@ define i64 @unsigned_sat_constant_i64_using_cmp_sum(i64 %x) {
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    li 4, -1
 ; CHECK-NEXT:    cmpld 5, 3
-; CHECK-NEXT:    isel 3, 4, 5, 0
+; CHECK-NEXT:    isellt 3, 4, 5
 ; CHECK-NEXT:    blr
   %a = add i64 %x, 42
   %c = icmp ugt i64 %x, %a
@@ -174,7 +174,7 @@ define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
 ; CHECK-NEXT:    addi 5, 3, 42
 ; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, -1
-; CHECK-NEXT:    isel 3, 3, 5, 1
+; CHECK-NEXT:    iselgt 3, 3, 5
 ; CHECK-NEXT:    blr
   %a = add i64 %x, 42
   %c = icmp ugt i64 %x, -43
@@ -185,11 +185,11 @@ define i64 @unsigned_sat_constant_i64_using_cmp_notval(i64 %x) {
 define i8 @unsigned_sat_variable_i8_using_min(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 24
 ; CHECK-NEXT:    clrlwi 7, 5, 24
 ; CHECK-NEXT:    cmplw 6, 7
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i8 %y, -1
@@ -207,7 +207,7 @@ define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    andi. 4, 3, 256
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i8 %x, %y
   %c = icmp ugt i8 %x, %a
@@ -218,13 +218,13 @@ define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
 define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 24
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    clrlwi 6, 6, 24
 ; CHECK-NEXT:    cmplw 7, 6
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i8 %y, -1
   %a = add i8 %x, %y
@@ -236,11 +236,11 @@ define i8 @unsigned_sat_variable_i8_using_cmp_notval(i8 %x, i8 %y) {
 define i16 @unsigned_sat_variable_i16_using_min(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    clrlwi 6, 3, 16
 ; CHECK-NEXT:    clrlwi 7, 5, 16
 ; CHECK-NEXT:    cmplw 6, 7
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i16 %y, -1
@@ -258,7 +258,7 @@ define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    andis. 4, 3, 1
 ; CHECK-NEXT:    li 4, -1
-; CHECK-NEXT:    isel 3, 3, 4, 2
+; CHECK-NEXT:    iseleq 3, 3, 4
 ; CHECK-NEXT:    blr
   %a = add i16 %x, %y
   %c = icmp ugt i16 %x, %a
@@ -269,13 +269,13 @@ define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
 define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    clrlwi 7, 3, 16
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    clrlwi 6, 6, 16
 ; CHECK-NEXT:    cmplw 7, 6
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i16 %y, -1
   %a = add i16 %x, %y
@@ -287,9 +287,9 @@ define i16 @unsigned_sat_variable_i16_using_cmp_notval(i16 %x, i16 %y) {
 define i32 @unsigned_sat_variable_i32_using_min(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_min:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 5, 4, 4
+; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    cmplw 3, 5
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i32 %y, -1
@@ -305,7 +305,7 @@ define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
 ; CHECK-NEXT:    add 4, 3, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmplw 4, 3
-; CHECK-NEXT:    isel 3, 5, 4, 0
+; CHECK-NEXT:    isellt 3, 5, 4
 ; CHECK-NEXT:    blr
   %a = add i32 %x, %y
   %c = icmp ugt i32 %x, %a
@@ -316,11 +316,11 @@ define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
 define i32 @unsigned_sat_variable_i32_using_cmp_notval(i32 %x, i32 %y) {
 ; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_notval:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 6, 4, 4
+; CHECK-NEXT:    not 6, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmplw 3, 6
 ; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i32 %y, -1
   %a = add i32 %x, %y
@@ -334,7 +334,7 @@ define i64 @unsigned_sat_variable_i64_using_min(i64 %x, i64 %y) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    not 5, 4
 ; CHECK-NEXT:    cmpld 3, 5
-; CHECK-NEXT:    isel 3, 3, 5, 0
+; CHECK-NEXT:    isellt 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %noty = xor i64 %y, -1
@@ -350,7 +350,7 @@ define i64 @unsigned_sat_variable_i64_using_cmp_sum(i64 %x, i64 %y) {
 ; CHECK-NEXT:    add 4, 3, 4
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmpld 4, 3
-; CHECK-NEXT:    isel 3, 5, 4, 0
+; CHECK-NEXT:    isellt 3, 5, 4
 ; CHECK-NEXT:    blr
   %a = add i64 %x, %y
   %c = icmp ugt i64 %x, %a
@@ -365,7 +365,7 @@ define i64 @unsigned_sat_variable_i64_using_cmp_notval(i64 %x, i64 %y) {
 ; CHECK-NEXT:    li 5, -1
 ; CHECK-NEXT:    cmpld 3, 6
 ; CHECK-NEXT:    add 3, 3, 4
-; CHECK-NEXT:    isel 3, 5, 3, 1
+; CHECK-NEXT:    iselgt 3, 5, 3
 ; CHECK-NEXT:    blr
   %noty = xor i64 %y, -1
   %a = add i64 %x, %y

test/CodeGen/PowerPC/select_const.ll

@@ -194,7 +194,7 @@ define i32 @select_C1_C2(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2:
@@ -217,7 +217,7 @@ define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_zeroext:
@@ -240,7 +240,7 @@ define i32 @select_C1_C2_signext(i1 signext %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 421
 ; ISEL-NEXT:    li 3, 42
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: select_C1_C2_signext:
@@ -265,7 +265,7 @@ define i8 @sel_constants_add_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 1
 ; ISEL-NEXT:    li 3, 28
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_add_constant:
@@ -289,7 +289,7 @@ define i8 @sel_constants_sub_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -9
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant:
@@ -313,7 +313,7 @@ define i8 @sel_constants_sub_constant_sel_constants(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 9
 ; ISEL-NEXT:    li 3, 2
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sub_constant_sel_constants:
@@ -337,7 +337,7 @@ define i8 @sel_constants_mul_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -20
 ; ISEL-NEXT:    li 3, 115
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_mul_constant:
@@ -360,7 +360,7 @@ define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_sdiv_constant:
@@ -370,7 +370,7 @@ define i8 @sel_constants_sdiv_constant(i1 %cond) {
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB25_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB25_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = sdiv i8 %sel, 5
@@ -382,7 +382,7 @@ define i8 @sdiv_constant_sel_constants(i1 %cond) {
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sdiv_constant_sel_constants:
@@ -392,7 +392,7 @@ define i8 @sdiv_constant_sel_constants(i1 %cond) {
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB26_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB26_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 121, i8 23
   %bo = sdiv i8 120, %sel
@@ -405,7 +405,7 @@ define i8 @sel_constants_udiv_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 50
 ; ISEL-NEXT:    li 3, 4
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_udiv_constant:
@@ -428,7 +428,7 @@ define i8 @udiv_constant_sel_constants(i1 %cond) {
 ; ISEL:       # %bb.0:
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 0, 3, 1
+; ISEL-NEXT:    iselgt 3, 0, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: udiv_constant_sel_constants:
@@ -438,7 +438,7 @@ define i8 @udiv_constant_sel_constants(i1 %cond) {
 ; NO_ISEL-NEXT:    bc 12, 1, .LBB28_1
 ; NO_ISEL-NEXT:    blr
 ; NO_ISEL-NEXT:  .LBB28_1:
-; NO_ISEL-NEXT:    addi 3, 0, 0
+; NO_ISEL-NEXT:    li 3, 0
 ; NO_ISEL-NEXT:    blr
   %sel = select i1 %cond, i8 -4, i8 23
   %bo = udiv i8 120, %sel
@@ -451,7 +451,7 @@ define i8 @sel_constants_srem_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -4
 ; ISEL-NEXT:    li 3, 3
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_srem_constant:
@@ -475,7 +475,7 @@ define i8 @srem_constant_sel_constants(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: srem_constant_sel_constants:
@@ -510,7 +510,7 @@ define i8 @urem_constant_sel_constants(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 120
 ; ISEL-NEXT:    li 3, 5
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: urem_constant_sel_constants:
@@ -545,7 +545,7 @@ define i8 @sel_constants_or_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -3
 ; ISEL-NEXT:    li 3, 23
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_or_constant:
@@ -569,7 +569,7 @@ define i8 @sel_constants_xor_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -7
 ; ISEL-NEXT:    li 3, 18
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_xor_constant:
@@ -593,7 +593,7 @@ define i8 @sel_constants_shl_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, -128
 ; ISEL-NEXT:    li 3, -32
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_shl_constant:
@@ -630,7 +630,7 @@ define i8 @sel_constants_lshr_constant(i1 %cond) {
 ; ISEL-NEXT:    andi. 3, 3, 1
 ; ISEL-NEXT:    li 4, 7
 ; ISEL-NEXT:    li 3, 0
-; ISEL-NEXT:    isel 3, 4, 3, 1
+; ISEL-NEXT:    iselgt 3, 4, 3
 ; ISEL-NEXT:    blr
 ;
 ; NO_ISEL-LABEL: sel_constants_lshr_constant:
@@ -694,7 +694,7 @@ define double @sel_constants_fadd_constant(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI42_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI42_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI42_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -725,7 +725,7 @@ define double @sel_constants_fsub_constant(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI43_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI43_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI43_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -756,7 +756,7 @@ define double @fsub_constant_sel_constants(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI44_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI44_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI44_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -787,7 +787,7 @@ define double @sel_constants_fmul_constant(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI45_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI45_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI45_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -818,7 +818,7 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI46_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI46_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI46_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -849,7 +849,7 @@ define double @fdiv_constant_sel_constants(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI47_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI47_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI47_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;
@@ -898,7 +898,7 @@ define double @frem_constant_sel_constants(i1 %cond) {
 ; ISEL-NEXT:    addis 3, 2, .LCPI49_1@toc@ha
 ; ISEL-NEXT:    addi 4, 4, .LCPI49_0@toc@l
 ; ISEL-NEXT:    addi 3, 3, .LCPI49_1@toc@l
-; ISEL-NEXT:    isel 3, 3, 4, 1
+; ISEL-NEXT:    iselgt 3, 3, 4
 ; ISEL-NEXT:    lfdx 1, 0, 3
 ; ISEL-NEXT:    blr
 ;

test/CodeGen/PowerPC/setcc-logic.ll

@@ -18,7 +18,7 @@ define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: all_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    or 3, 3, 4
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
@@ -100,7 +100,7 @@ define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q)  {
 ; CHECK-LABEL: any_sign_bits_clear:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    and 3, 3, 4
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %a = icmp sgt i32 %P, -1
@@ -499,7 +499,7 @@ define i1 @and_icmps_const_1bit_diff(i32 %x) {
 ; CHECK-NEXT:    addi 3, 3, -4625
 ; CHECK-NEXT:    rlwinm 3, 3, 0, 28, 26
 ; CHECK-NEXT:    cntlzw 3, 3
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    rlwinm 3, 3, 27, 31, 31
 ; CHECK-NEXT:    blr
   %a = icmp ne i32 %x, 4625

test/CodeGen/PowerPC/shift128.ll

@@ -26,7 +26,7 @@ define i128 @lshr(i128 %x, i128 %y) {
 ; CHECK-DAG: or [[R5:[0-9]+]], [[R2]], [[R3]]
 ; CHECK-DAG: cmpwi [[R1]], 1
 ; CHECK-DAG: srad 4, 4, 5
-; CHECK-DAG: isel 3, [[R5]], [[R4]], 0
+; CHECK-DAG: isellt 3, [[R5]], [[R4]]
 ; CHECK: blr
 define i128 @ashr(i128 %x, i128 %y) {
   %r = ashr i128 %x, %y

test/CodeGen/PowerPC/signbit-shift.ll

@@ -6,7 +6,7 @@
 define i32 @zext_ifpos(i32 %x) {
 ; CHECK-LABEL: zext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srwi 3, 3, 31
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
@@ -48,7 +48,7 @@ define i32 @sel_ifpos_tval_bigger(i32 %x) {
 ; CHECK-NEXT:    li 4, 41
 ; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 42, i32 41
@@ -58,7 +58,7 @@ define i32 @sel_ifpos_tval_bigger(i32 %x) {
 define i32 @sext_ifpos(i32 %x) {
 ; CHECK-LABEL: sext_ifpos:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    nor 3, 3, 3
+; CHECK-NEXT:    not 3, 3
 ; CHECK-NEXT:    srawi 3, 3, 31
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
@@ -100,7 +100,7 @@ define i32 @sel_ifpos_fval_bigger(i32 %x) {
 ; CHECK-NEXT:    li 4, 42
 ; CHECK-NEXT:    cmpwi 3, -1
 ; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    isel 3, 3, 4, 1
+; CHECK-NEXT:    iselgt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp sgt i32 %x, -1
   %r = select i1 %c, i32 41, i32 42
@@ -137,7 +137,7 @@ define i32 @sel_ifneg_tval_bigger(i32 %x) {
 ; CHECK-NEXT:    li 4, 41
 ; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    li 3, 42
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 42, i32 41
@@ -172,7 +172,7 @@ define i32 @sel_ifneg_fval_bigger(i32 %x) {
 ; CHECK-NEXT:    li 4, 42
 ; CHECK-NEXT:    cmpwi 3, 0
 ; CHECK-NEXT:    li 3, 41
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    blr
   %c = icmp slt i32 %x, 0
   %r = select i1 %c, i32 41, i32 42

test/CodeGen/PowerPC/sms-cpy-1.ll

@@ -15,11 +15,11 @@ define void @print_res() nounwind {
 ; CHECK-NEXT:    clrldi 4, 3, 32
 ; CHECK-NEXT:    cmplwi 3, 1
 ; CHECK-NEXT:    li 3, 1
-; CHECK-NEXT:    isel 3, 4, 3, 1
+; CHECK-NEXT:    iselgt 3, 4, 3
 ; CHECK-NEXT:    li 4, 2
 ; CHECK-NEXT:    addi 3, 3, -1
 ; CHECK-NEXT:    cmpldi 3, 2
-; CHECK-NEXT:    isel 3, 3, 4, 0
+; CHECK-NEXT:    isellt 3, 3, 4
 ; CHECK-NEXT:    li 4, 0
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    li 5, 0
@@ -44,7 +44,7 @@ define void @print_res() nounwind {
 ; CHECK-NEXT:    lbz 5, 0(5)
 ; CHECK-NEXT:    addi 3, 3, 1
 ; CHECK-NEXT:    bdz .LBB0_4
-; CHECK-NEXT:  .LBB0_3: #
+; CHECK-NEXT:  .LBB0_3:
 ; CHECK-NEXT:    clrldi 10, 8, 32
 ; CHECK-NEXT:    cntlzw 9, 6
 ; CHECK-NEXT:    xori 6, 5, 84

test/CodeGen/PowerPC/sms-phi-2.ll

@@ -13,21 +13,21 @@ define void @phi2(i32, i32, i8*) local_unnamed_addr {
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    divw 9, 8, 4
 ; CHECK-NEXT:    mullw 7, 8, 4
-; CHECK-NEXT:    subf 3, 7, 3
+; CHECK-NEXT:    sub 3, 3, 7
 ; CHECK-NEXT:    cmplwi 3, 10
-; CHECK-NEXT:    isel 7, 6, 5, 0
+; CHECK-NEXT:    isellt 7, 6, 5
 ; CHECK-NEXT:    add 3, 7, 3
 ; CHECK-NEXT:    stbu 3, -1(7)
 ; CHECK-NEXT:    mr 3, 8
 ; CHECK-NEXT:    bdz .LBB0_3
 ; CHECK-NEXT:    .p2align 4
-; CHECK-NEXT:  .LBB0_2: #
+; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    mr 3, 9
 ; CHECK-NEXT:    mullw 9, 9, 4
 ; CHECK-NEXT:    divw 10, 3, 4
-; CHECK-NEXT:    subf 8, 9, 8
+; CHECK-NEXT:    sub 8, 8, 9
 ; CHECK-NEXT:    cmplwi 8, 10
-; CHECK-NEXT:    isel 9, 6, 5, 0
+; CHECK-NEXT:    isellt 9, 6, 5
 ; CHECK-NEXT:    add 8, 9, 8
 ; CHECK-NEXT:    mr 9, 10
 ; CHECK-NEXT:    stbu 8, -1(7)
@@ -40,9 +40,9 @@ define void @phi2(i32, i32, i8*) local_unnamed_addr {
 ; CHECK-NEXT:    # implicit-def: $x7
 ; CHECK-NEXT:  .LBB0_5:
 ; CHECK-NEXT:    mullw 4, 8, 4
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    cmplwi 3, 10
-; CHECK-NEXT:    isel 4, 6, 5, 0
+; CHECK-NEXT:    isellt 4, 6, 5
 ; CHECK-NEXT:    add 3, 4, 3
 ; CHECK-NEXT:    stbu 3, -1(7)
 ; CHECK-NEXT:    blr

test/CodeGen/PowerPC/spe.ll

@@ -272,7 +272,7 @@ define i1 @test_fcmpuno(float %a, float %b) {
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB13_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno float %a, %b
@@ -291,7 +291,7 @@ define i1 @test_fcmpord(float %a, float %b) {
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB14_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord float %a, %b
@@ -312,7 +312,7 @@ define i1 @test_fcmpueq(float %a, float %b) {
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB15_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ueq float %a, %b
@@ -333,7 +333,7 @@ define i1 @test_fcmpne(float %a, float %b) {
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one float %a, %b
@@ -418,7 +418,7 @@ define i1 @test_fcmpult(float %a, float %b) {
 ; CHECK-NEXT:    ori 3, 5, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB19_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ult float %a, %b
@@ -691,7 +691,7 @@ define i1 @test_dcmpuno(double %a, double %b) {
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB35_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp uno double %a, %b
@@ -712,7 +712,7 @@ define i1 @test_dcmpord(double %a, double %b) {
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB36_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp ord double %a, %b
@@ -952,7 +952,7 @@ define i1 @test_dcmpne(double %a, double %b) {
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB43_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp one double %a, %b
@@ -1083,7 +1083,7 @@ define i1 @test_dcmpge(double %a, double %b) {
 ; CHECK-NEXT:    ori 3, 7, 0
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB47_2: # %entry
-; CHECK-NEXT:    addi 3, 0, 0
+; CHECK-NEXT:    li 3, 0
 ; CHECK-NEXT:    blr
   entry:
   %r = fcmp oge double %a, %b

test/CodeGen/PowerPC/srem-lkk.ll

@@ -13,7 +13,7 @@ define i32 @fold_srem_positive_odd(i32 %x) {
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
   ret i32 %1
@@ -30,7 +30,7 @@ define i32 @fold_srem_positive_even(i32 %x) {
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 1060
   ret i32 %1
@@ -47,7 +47,7 @@ define i32 @fold_srem_negative_odd(i32 %x) {
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -723
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -723
   ret i32 %1
@@ -64,7 +64,7 @@ define i32 @fold_srem_negative_even(i32 %x) {
 ; CHECK-NEXT:    srawi 4, 4, 8
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 4, 4, -22981
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, -22981
   ret i32 %1
@@ -83,7 +83,7 @@ define i32 @combine_srem_sdiv(i32 %x) {
 ; CHECK-NEXT:    srawi 4, 4, 6
 ; CHECK-NEXT:    add 4, 4, 5
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 95
@@ -99,7 +99,7 @@ define i32 @dont_fold_srem_power_of_two(i32 %x) {
 ; CHECK-NEXT:    srawi 4, 3, 6
 ; CHECK-NEXT:    addze 4, 4
 ; CHECK-NEXT:    slwi 4, 4, 6
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = srem i32 %x, 64
   ret i32 %1

test/CodeGen/PowerPC/srem-vector-lkk.ll

@@ -23,20 +23,20 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 31710
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    extsh r4, r3
 ; P9LE-NEXT:    ori r5, r5, 63421
 ; P9LE-NEXT:    mulhw r5, r4, r5
-; P9LE-NEXT:    subf r4, r4, r5
+; P9LE-NEXT:    sub r4, r5, r4
 ; P9LE-NEXT:    srwi r5, r4, 31
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 21399
 ; P9LE-NEXT:    mulli r4, r4, -124
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
@@ -49,7 +49,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -16728
 ; P9LE-NEXT:    mulli r4, r4, 98
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
@@ -61,7 +61,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 8
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, -1003
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -78,12 +78,12 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    ori r4, r4, 63421
 ; P9BE-NEXT:    extsh r3, r3
 ; P9BE-NEXT:    mulhw r4, r3, r4
-; P9BE-NEXT:    subf r4, r3, r4
+; P9BE-NEXT:    sub r4, r4, r3
 ; P9BE-NEXT:    srwi r5, r4, 31
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -124
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
@@ -97,7 +97,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -16728
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -110,7 +110,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 8
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, -1003
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
@@ -124,7 +124,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 5
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 98
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
@@ -158,7 +158,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P8LE-NEXT:    srwi r12, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 5
 ; P8LE-NEXT:    add r9, r9, r0
-; P8LE-NEXT:    subf r10, r11, r10
+; P8LE-NEXT:    sub r10, r10, r11
 ; P8LE-NEXT:    add r3, r3, r12
 ; P8LE-NEXT:    srwi r11, r9, 31
 ; P8LE-NEXT:    srawi r9, r9, 6
@@ -173,11 +173,11 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P8LE-NEXT:    mulli r8, r8, -1003
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    mulli r10, r10, -124
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
-; P8LE-NEXT:    subf r5, r8, r6
+; P8LE-NEXT:    sub r5, r6, r8
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r9, r7
+; P8LE-NEXT:    sub r3, r7, r9
-; P8LE-NEXT:    subf r4, r10, r4
+; P8LE-NEXT:    sub r4, r4, r10
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
@@ -217,7 +217,7 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P8BE-NEXT:    srawi r3, r3, 8
 ; P8BE-NEXT:    add r3, r3, r11
 ; P8BE-NEXT:    srwi r11, r8, 31
-; P8BE-NEXT:    subf r9, r7, r9
+; P8BE-NEXT:    sub r9, r9, r7
 ; P8BE-NEXT:    srawi r8, r8, 5
 ; P8BE-NEXT:    add r10, r10, r4
 ; P8BE-NEXT:    add r8, r8, r11
@@ -231,13 +231,13 @@ define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {
 ; P8BE-NEXT:    add r10, r10, r11
 ; P8BE-NEXT:    mulli r9, r9, -124
 ; P8BE-NEXT:    mulli r10, r10, 95
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    subf r5, r8, r6
+; P8BE-NEXT:    sub r5, r6, r8
 ; P8BE-NEXT:    mtvsrd v2, r3
-; P8BE-NEXT:    subf r6, r9, r7
+; P8BE-NEXT:    sub r6, r7, r9
 ; P8BE-NEXT:    sldi r3, r5, 48
-; P8BE-NEXT:    subf r4, r10, r4
+; P8BE-NEXT:    sub r4, r4, r10
 ; P8BE-NEXT:    mtvsrd v3, r3
 ; P8BE-NEXT:    sldi r3, r6, 48
 ; P8BE-NEXT:    sldi r4, r4, 48
@@ -265,7 +265,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -276,7 +276,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
@@ -288,7 +288,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
@@ -300,7 +300,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -322,7 +322,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
@@ -334,7 +334,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
@@ -346,7 +346,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -359,7 +359,7 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
@@ -404,17 +404,17 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P8LE-NEXT:    srwi r11, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 6
 ; P8LE-NEXT:    mulli r10, r10, 95
-; P8LE-NEXT:    subf r5, r8, r5
+; P8LE-NEXT:    sub r5, r5, r8
 ; P8LE-NEXT:    add r3, r3, r11
 ; P8LE-NEXT:    mtfprd f0, r5
 ; P8LE-NEXT:    mulli r3, r3, 95
-; P8LE-NEXT:    subf r6, r9, r6
+; P8LE-NEXT:    sub r6, r6, r9
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxswapd v2, vs0
-; P8LE-NEXT:    subf r5, r10, r7
+; P8LE-NEXT:    sub r5, r7, r10
 ; P8LE-NEXT:    mtfprd f2, r5
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r3, r4
+; P8LE-NEXT:    sub r3, r4, r3
 ; P8LE-NEXT:    mtfprd f3, r3
 ; P8LE-NEXT:    xxswapd v4, vs2
 ; P8LE-NEXT:    vmrglh v2, v3, v2
@@ -458,16 +458,16 @@ define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {
 ; P8BE-NEXT:    srwi r11, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 6
 ; P8BE-NEXT:    mulli r10, r10, 95
-; P8BE-NEXT:    subf r5, r8, r5
+; P8BE-NEXT:    sub r5, r5, r8
 ; P8BE-NEXT:    add r3, r3, r11
 ; P8BE-NEXT:    sldi r5, r5, 48
 ; P8BE-NEXT:    mulli r3, r3, 95
-; P8BE-NEXT:    subf r6, r9, r6
+; P8BE-NEXT:    sub r6, r6, r9
 ; P8BE-NEXT:    mtvsrd v2, r5
 ; P8BE-NEXT:    sldi r6, r6, 48
-; P8BE-NEXT:    subf r7, r10, r7
+; P8BE-NEXT:    sub r7, r7, r10
 ; P8BE-NEXT:    mtvsrd v3, r6
-; P8BE-NEXT:    subf r3, r3, r4
+; P8BE-NEXT:    sub r3, r4, r3
 ; P8BE-NEXT:    sldi r4, r7, 48
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r3, r3, 48
@@ -496,7 +496,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    mulli r6, r4, 95
-; P9LE-NEXT:    subf r3, r6, r3
+; P9LE-NEXT:    sub r3, r3, r6
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -507,7 +507,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r6, r6, 6
 ; P9LE-NEXT:    add r6, r6, r7
 ; P9LE-NEXT:    mulli r7, r6, 95
-; P9LE-NEXT:    subf r3, r7, r3
+; P9LE-NEXT:    sub r3, r3, r7
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
@@ -519,7 +519,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r7, r7, 6
 ; P9LE-NEXT:    add r7, r7, r8
 ; P9LE-NEXT:    mulli r8, r7, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
@@ -531,7 +531,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r5, r5, 6
 ; P9LE-NEXT:    add r5, r5, r8
 ; P9LE-NEXT:    mulli r8, r5, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -565,7 +565,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    mulli r6, r4, 95
-; P9BE-NEXT:    subf r3, r6, r3
+; P9BE-NEXT:    sub r3, r3, r6
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
@@ -577,7 +577,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r6, r6, 6
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    mulli r7, r6, 95
-; P9BE-NEXT:    subf r3, r7, r3
+; P9BE-NEXT:    sub r3, r3, r7
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
@@ -589,7 +589,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r7, r7, 6
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    mulli r8, r7, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -602,7 +602,7 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r5, r5, 6
 ; P9BE-NEXT:    add r5, r5, r8
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    sldi r3, r4, 48
@@ -668,14 +668,14 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    subf r3, r12, r3
+; P8LE-NEXT:    sub r3, r3, r12
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r6, r11, r6
+; P8LE-NEXT:    sub r6, r6, r11
 ; P8LE-NEXT:    xxswapd v6, vs3
-; P8LE-NEXT:    subf r3, r9, r7
+; P8LE-NEXT:    sub r3, r7, r9
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f4, r3
-; P8LE-NEXT:    subf r3, r4, r5
+; P8LE-NEXT:    sub r3, r5, r4
 ; P8LE-NEXT:    mtfprd f5, r3
 ; P8LE-NEXT:    xxswapd v4, vs1
 ; P8LE-NEXT:    vmrglh v2, v3, v2
@@ -732,15 +732,15 @@ define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {
 ; P8BE-NEXT:    mtvsrd v2, r8
 ; P8BE-NEXT:    mulli r8, r10, 95
 ; P8BE-NEXT:    sldi r10, r10, 48
-; P8BE-NEXT:    subf r3, r12, r3
+; P8BE-NEXT:    sub r3, r3, r12
 ; P8BE-NEXT:    mtvsrd v4, r10
-; P8BE-NEXT:    subf r6, r0, r6
+; P8BE-NEXT:    sub r6, r6, r0
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    subf r3, r9, r5
+; P8BE-NEXT:    sub r3, r5, r9
-; P8BE-NEXT:    subf r7, r8, r7
+; P8BE-NEXT:    sub r7, r7, r8
 ; P8BE-NEXT:    mtvsrd v5, r6
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    sldi r5, r7, 48
@@ -771,7 +771,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 6
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -779,7 +779,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 5
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 5
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
@@ -794,7 +794,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 6
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -802,7 +802,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 3
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 3
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -819,7 +819,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r3, 5
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 5
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 0
@@ -828,7 +828,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r3, 6
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 6
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -21386
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -842,7 +842,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 6
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -852,7 +852,7 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r3, 3
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 3
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
@@ -879,23 +879,23 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P8LE-NEXT:    slwi r8, r8, 6
 ; P8LE-NEXT:    add r3, r3, r6
 ; P8LE-NEXT:    addze r6, r10
-; P8LE-NEXT:    subf r7, r8, r7
+; P8LE-NEXT:    sub r7, r7, r8
 ; P8LE-NEXT:    srwi r10, r3, 31
 ; P8LE-NEXT:    srawi r3, r3, 6
 ; P8LE-NEXT:    mtfprd f0, r7
 ; P8LE-NEXT:    slwi r6, r6, 5
 ; P8LE-NEXT:    add r3, r3, r10
 ; P8LE-NEXT:    extsh r10, r4
-; P8LE-NEXT:    subf r6, r6, r9
+; P8LE-NEXT:    sub r6, r9, r6
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    srawi r8, r10, 3
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    addze r7, r8
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
 ; P8LE-NEXT:    slwi r5, r7, 3
-; P8LE-NEXT:    subf r4, r5, r4
+; P8LE-NEXT:    sub r4, r4, r5
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v4, vs2
@@ -925,21 +925,21 @@ define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {
 ; P8BE-NEXT:    slwi r8, r8, 5
 ; P8BE-NEXT:    add r3, r3, r5
 ; P8BE-NEXT:    addze r9, r9
-; P8BE-NEXT:    subf r6, r8, r6
+; P8BE-NEXT:    sub r6, r6, r8
 ; P8BE-NEXT:    srwi r10, r3, 31
 ; P8BE-NEXT:    srawi r3, r3, 6
 ; P8BE-NEXT:    slwi r8, r9, 6
 ; P8BE-NEXT:    add r3, r3, r10
 ; P8BE-NEXT:    srawi r9, r4, 3
-; P8BE-NEXT:    subf r7, r8, r7
+; P8BE-NEXT:    sub r7, r7, r8
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    addze r8, r9
 ; P8BE-NEXT:    mtvsrd v2, r6
 ; P8BE-NEXT:    slwi r6, r8, 3
-; P8BE-NEXT:    subf r4, r6, r4
+; P8BE-NEXT:    sub r4, r4, r6
 ; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    sldi r5, r7, 48
 ; P8BE-NEXT:    mtvsrd v5, r4
 ; P8BE-NEXT:    sldi r3, r3, 48
@@ -969,7 +969,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, -19946
 ; P9LE-NEXT:    mulli r4, r4, 654
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    ori r5, r5, 17097
@@ -983,7 +983,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
@@ -995,7 +995,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -1017,7 +1017,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
@@ -1030,7 +1030,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -14230
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -1044,7 +1044,7 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 9
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 654
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    li r3, 0
@@ -1089,10 +1089,10 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P8LE-NEXT:    add r8, r8, r9
 ; P8LE-NEXT:    mulli r7, r7, 23
 ; P8LE-NEXT:    mulli r8, r8, 654
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r7, r6
+; P8LE-NEXT:    sub r3, r6, r7
-; P8LE-NEXT:    subf r4, r8, r4
+; P8LE-NEXT:    sub r4, r4, r8
 ; P8LE-NEXT:    mtfprd f1, r3
 ; P8LE-NEXT:    mtfprd f2, r4
 ; P8LE-NEXT:    xxswapd v2, vs0
@@ -1136,12 +1136,12 @@ define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {
 ; P8BE-NEXT:    mulli r6, r6, 23
 ; P8BE-NEXT:    li r9, 0
 ; P8BE-NEXT:    mulli r8, r8, 654
-; P8BE-NEXT:    subf r4, r5, r4
+; P8BE-NEXT:    sub r4, r4, r5
 ; P8BE-NEXT:    sldi r5, r9, 48
 ; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    subf r5, r6, r7
+; P8BE-NEXT:    sub r5, r7, r6
 ; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    subf r3, r8, r3
+; P8BE-NEXT:    sub r3, r3, r8
 ; P8BE-NEXT:    mtvsrd v3, r4
 ; P8BE-NEXT:    sldi r4, r5, 48
 ; P8BE-NEXT:    sldi r3, r3, 48
@@ -1171,7 +1171,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    lis r5, 24749
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -1182,7 +1182,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 11
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
@@ -1191,7 +1191,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9LE-NEXT:    srawi r4, r4, 15
 ; P9LE-NEXT:    addze r4, r4
 ; P9LE-NEXT:    slwi r4, r4, 15
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
@@ -1214,7 +1214,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 4
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 24749
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
@@ -1227,7 +1227,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r4, 11
 ; P9BE-NEXT:    add r4, r4, r5
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
@@ -1236,7 +1236,7 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P9BE-NEXT:    srawi r4, r3, 15
 ; P9BE-NEXT:    addze r4, r4
 ; P9BE-NEXT:    slwi r4, r4, 15
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    li r3, 0
@@ -1274,12 +1274,12 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P8LE-NEXT:    extsh r8, r3
 ; P8LE-NEXT:    mulli r5, r5, 23
 ; P8LE-NEXT:    srawi r8, r8, 15
-; P8LE-NEXT:    subf r4, r4, r6
+; P8LE-NEXT:    sub r4, r6, r4
 ; P8LE-NEXT:    addze r6, r8
 ; P8LE-NEXT:    mtfprd f0, r4
 ; P8LE-NEXT:    slwi r4, r6, 15
-; P8LE-NEXT:    subf r5, r5, r7
+; P8LE-NEXT:    sub r5, r7, r5
-; P8LE-NEXT:    subf r3, r4, r3
+; P8LE-NEXT:    sub r3, r3, r4
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    mtfprd f2, r3
@@ -1316,14 +1316,14 @@ define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
 ; P8BE-NEXT:    li r8, 0
 ; P8BE-NEXT:    mulli r5, r5, 23
 ; P8BE-NEXT:    srawi r9, r3, 15
-; P8BE-NEXT:    subf r4, r4, r6
+; P8BE-NEXT:    sub r4, r6, r4
 ; P8BE-NEXT:    sldi r6, r8, 48
 ; P8BE-NEXT:    addze r8, r9
 ; P8BE-NEXT:    mtvsrd v2, r6
 ; P8BE-NEXT:    slwi r6, r8, 15
 ; P8BE-NEXT:    sldi r4, r4, 48
-; P8BE-NEXT:    subf r5, r5, r7
+; P8BE-NEXT:    sub r5, r7, r5
-; P8BE-NEXT:    subf r3, r6, r3
+; P8BE-NEXT:    sub r3, r3, r6
 ; P8BE-NEXT:    mtvsrd v3, r4
 ; P8BE-NEXT:    sldi r4, r5, 48
 ; P8BE-NEXT:    sldi r3, r3, 48

test/CodeGen/PowerPC/stack-guard-reassign.ll

@@ -8,7 +8,7 @@
 ; CHECK-NEXT: lis 0, -2
 ; CHECK-NEXT: ori 0, 0, 65488
 ; CHECK-NEXT: stwux 1, 1, 0
-; CHECK-NEXT: subf 0, 0, 1
+; CHECK-NEXT: sub 0, 1, 0
 ; CHECK-NEXT: lis 4, __stack_chk_guard@ha
 ; CHECK-NEXT: lwz 5, __stack_chk_guard@l(4)
 ; CHECK-NEXT: lis 6, 1

test/CodeGen/PowerPC/stack-realign.ll

@@ -82,7 +82,7 @@ entry:
 ; CHECK-32-DAG: stw [[LR]], 4(1)
 ; CHECK-32-DAG: subfic 0, [[REG]], -64
 ; CHECK-32: stwux 1, 1, 0
-; CHECK-32: subf 0, 0, 1
+; CHECK-32: sub 0, 1, 0
 ; CHECK-32: addic 0, 0, -4
 ; CHECK-32: stwx 31, 0, 0
 ; CHECK-32: addic 0, 0, -4
@@ -95,7 +95,7 @@ entry:
 ; CHECK-32-PIC-DAG: stw [[LR]], 4(1)
 ; CHECK-32-PIC-DAG: subfic 0, [[REG]], -64
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
@@ -143,9 +143,9 @@ entry:
 ; CHECK-32-DAG: mflr [[LR:[0-9]+]]
 ; CHECK-32-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-DAG: stw [[LR]], 4(1)
-; CHECK-32-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK-32-DAG: subc 0, [[REG2]], [[REG3]]
 ; CHECK-32:     stwux 1, 1, 0
-; CHECK-32:     subf 0, 0, 1
+; CHECK-32:     sub 0, 1, 0
 ; CHECK-32:     addic 0, 0, -4
 ; CHECK-32:     stwx 31, 0, 0
 ; CHECK-32:     addic 0, 0, -4
@@ -161,9 +161,9 @@ entry:
 ; CHECK-32-PIC-DAG: mflr {{[0-9]+}}
 ; CHECK-32-PIC-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51904
 ; CHECK-32-PIC-DAG: stw 0, 4(1)
-; CHECK-32-PIC-DAG: subfc 0, [[REG3]], [[REG2]]
+; CHECK-32-PIC-DAG: subc 0, [[REG2]], [[REG3]]
 ; CHECK-32-PIC:     stwux 1, 1, 0
-; CHECK-32-PIC:     subf 0, 0, 1
+; CHECK-32-PIC:     sub 0, 1, 0
 ; CHECK-32-PIC:     addic 0, 0, -4
 ; CHECK-32-PIC:     stwx 31, 0, 0
 ; CHECK-32-PIC:     addic 0, 0, -8

test/CodeGen/PowerPC/store-combine.ll

@@ -188,7 +188,7 @@ define void @store_i64_by_i8_bswap_uses(i32 signext %t, i8* %p) {
 ; CHECK-PPC64LE-LABEL: store_i64_by_i8_bswap_uses:
 ; CHECK-PPC64LE:       # %bb.0: # %entry
 ; CHECK-PPC64LE-NEXT:    slwi 5, 3, 3
-; CHECK-PPC64LE-NEXT:    subf 3, 3, 5
+; CHECK-PPC64LE-NEXT:    sub 3, 5, 3
 ; CHECK-PPC64LE-NEXT:    extsw 3, 3
 ; CHECK-PPC64LE-NEXT:    stdbrx 3, 0, 4
 ; CHECK-PPC64LE-NEXT:    blr
@@ -196,7 +196,7 @@ define void @store_i64_by_i8_bswap_uses(i32 signext %t, i8* %p) {
 ; CHECK-PPC64-LABEL: store_i64_by_i8_bswap_uses:
 ; CHECK-PPC64:       # %bb.0: # %entry
 ; CHECK-PPC64-NEXT:    slwi 5, 3, 3
-; CHECK-PPC64-NEXT:    subf 3, 3, 5
+; CHECK-PPC64-NEXT:    sub 3, 5, 3
 ; CHECK-PPC64-NEXT:    extsw 3, 3
 ; CHECK-PPC64-NEXT:    stdx 3, 0, 4
 ; CHECK-PPC64-NEXT:    blr

test/CodeGen/PowerPC/sub-of-not.ll

@@ -406,13 +406,13 @@ define <4 x i32> @vector_i128_i32(<4 x i32> %x, <4 x i32> %y) nounwind {
 define <2 x i64> @vector_i128_i64(<2 x i64> %x, <2 x i64> %y) nounwind {
 ; PPC32-LABEL: vector_i128_i64:
 ; PPC32:       # %bb.0:
-; PPC32-NEXT:    nor 4, 4, 4
+; PPC32-NEXT:    not 4, 4
-; PPC32-NEXT:    nor 3, 3, 3
+; PPC32-NEXT:    not 3, 3
-; PPC32-NEXT:    subfc 4, 4, 8
+; PPC32-NEXT:    subc 4, 8, 4
-; PPC32-NEXT:    nor 6, 6, 6
+; PPC32-NEXT:    not 6, 6
 ; PPC32-NEXT:    subfe 3, 3, 7
-; PPC32-NEXT:    nor 5, 5, 5
+; PPC32-NEXT:    not 5, 5
-; PPC32-NEXT:    subfc 6, 6, 10
+; PPC32-NEXT:    subc 6, 10, 6
 ; PPC32-NEXT:    subfe 5, 5, 9
 ; PPC32-NEXT:    blr
 ;

test/CodeGen/PowerPC/subc.ll

@@ -1,6 +1,6 @@
 ; All of these should be codegen'd without loading immediates
 ; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -o %t
-; RUN: grep subfc %t | count 1
+; RUN: grep subc %t | count 1
 ; RUN: grep subfe %t | count 1
 ; RUN: grep subfze %t | count 1
 ; RUN: grep subfme %t | count 1

test/CodeGen/PowerPC/subreg-postra.ll

@@ -150,7 +150,7 @@ wait_on_buffer.exit1319:                          ; preds = %while.body392
 ; CHECK: andi.
 ; CHECK: crmove
 ; CHECK: stdcx.
-; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}},
+; CHECK: iselgt {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: ori 30, 3, 0
 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]

test/CodeGen/PowerPC/umulo-128-legalisation-lowering.ll

@@ -29,7 +29,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; PPC64-NEXT:    ori 5, 7, 0
 ; PPC64-NEXT:    blr
 ; PPC64-NEXT:  .LBB0_2: # %start
-; PPC64-NEXT:    addi 5, 0, 0
+; PPC64-NEXT:    li 5, 0
 ; PPC64-NEXT:    blr
 ;
 ; PPC32-LABEL: muloti_test:
@@ -130,7 +130,7 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
 ; PPC32-NEXT:    ori 7, 3, 0
 ; PPC32-NEXT:    b .LBB0_3
 ; PPC32-NEXT:  .LBB0_2: # %start
-; PPC32-NEXT:    addi 7, 0, 0
+; PPC32-NEXT:    li 7, 0
 ; PPC32-NEXT:  .LBB0_3: # %start
 ; PPC32-NEXT:    mr 3, 8
 ; PPC32-NEXT:    mtcrf 32, 12 # cr2

test/CodeGen/PowerPC/urem-lkk.ll

@@ -8,12 +8,12 @@ define i32 @fold_urem_positive_odd(i32 %x) {
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 4, 4, 95
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95
   ret i32 %1
@@ -28,7 +28,7 @@ define i32 @fold_urem_positive_even(i32 %x) {
 ; CHECK-NEXT:    mulhwu 4, 3, 4
 ; CHECK-NEXT:    srwi 4, 4, 10
 ; CHECK-NEXT:    mulli 4, 4, 1060
-; CHECK-NEXT:    subf 3, 4, 3
+; CHECK-NEXT:    sub 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 1060
   ret i32 %1
@@ -42,12 +42,12 @@ define i32 @combine_urem_udiv(i32 %x) {
 ; CHECK-NEXT:    lis 4, 22765
 ; CHECK-NEXT:    ori 4, 4, 8969
 ; CHECK-NEXT:    mulhwu 4, 3, 4
-; CHECK-NEXT:    subf 5, 4, 3
+; CHECK-NEXT:    sub 5, 3, 4
 ; CHECK-NEXT:    srwi 5, 5, 1
 ; CHECK-NEXT:    add 4, 5, 4
 ; CHECK-NEXT:    srwi 4, 4, 6
 ; CHECK-NEXT:    mulli 5, 4, 95
-; CHECK-NEXT:    subf 3, 5, 3
+; CHECK-NEXT:    sub 3, 3, 5
 ; CHECK-NEXT:    add 3, 3, 4
 ; CHECK-NEXT:    blr
   %1 = urem i32 %x, 95

test/CodeGen/PowerPC/urem-vector-lkk.ll

@@ -21,7 +21,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 2287
 ; P9LE-NEXT:    srwi r4, r4, 5
 ; P9LE-NEXT:    mulli r4, r4, 98
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -31,7 +31,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 16913
 ; P9LE-NEXT:    srwi r4, r4, 8
 ; P9LE-NEXT:    mulli r4, r4, 1003
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
@@ -42,19 +42,19 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    srwi r4, r4, 2
 ; P9LE-NEXT:    mulli r4, r4, 124
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 0
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r4, r5
-; P9LE-NEXT:    subf r4, r5, r4
+; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -73,7 +73,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 8
 ; P9BE-NEXT:    mulli r4, r4, 1003
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, 21399
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
@@ -84,7 +84,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 5
 ; P9BE-NEXT:    mulli r4, r4, 98
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
@@ -97,7 +97,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 2
 ; P9BE-NEXT:    mulli r3, r3, 124
-; P9BE-NEXT:    subf r3, r3, r4
+; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    lis r4, 22765
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -106,12 +106,12 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    mulhwu r4, r3, r4
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
@@ -142,7 +142,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P8LE-NEXT:    ori r11, r11, 16913
 ; P8LE-NEXT:    rlwinm r12, r4, 30, 18, 31
 ; P8LE-NEXT:    mulhwu r11, r12, r11
-; P8LE-NEXT:    subf r9, r3, r9
+; P8LE-NEXT:    sub r9, r9, r3
 ; P8LE-NEXT:    srwi r9, r9, 1
 ; P8LE-NEXT:    srwi r7, r7, 5
 ; P8LE-NEXT:    add r3, r9, r3
@@ -153,11 +153,11 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P8LE-NEXT:    mulli r9, r9, 1003
 ; P8LE-NEXT:    mulli r3, r3, 95
 ; P8LE-NEXT:    mulli r10, r10, 124
-; P8LE-NEXT:    subf r5, r7, r5
+; P8LE-NEXT:    sub r5, r5, r7
-; P8LE-NEXT:    subf r7, r9, r8
+; P8LE-NEXT:    sub r7, r8, r9
 ; P8LE-NEXT:    mtfprd f0, r5
-; P8LE-NEXT:    subf r3, r3, r6
+; P8LE-NEXT:    sub r3, r6, r3
-; P8LE-NEXT:    subf r4, r10, r4
+; P8LE-NEXT:    sub r4, r4, r10
 ; P8LE-NEXT:    mtfprd f1, r7
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
@@ -194,7 +194,7 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r9, r8, r9
 ; P8BE-NEXT:    mulhwu r10, r11, r10
-; P8BE-NEXT:    subf r11, r3, r6
+; P8BE-NEXT:    sub r11, r6, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r7, r7, 8
 ; P8BE-NEXT:    add r3, r11, r3
@@ -205,11 +205,11 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; P8BE-NEXT:    mulli r9, r9, 98
 ; P8BE-NEXT:    mulli r3, r3, 95
 ; P8BE-NEXT:    mulli r10, r10, 124
-; P8BE-NEXT:    subf r5, r7, r5
+; P8BE-NEXT:    sub r5, r5, r7
-; P8BE-NEXT:    subf r7, r9, r8
+; P8BE-NEXT:    sub r7, r8, r9
 ; P8BE-NEXT:    sldi r5, r5, 48
-; P8BE-NEXT:    subf r3, r3, r6
+; P8BE-NEXT:    sub r3, r6, r3
-; P8BE-NEXT:    subf r4, r10, r4
+; P8BE-NEXT:    sub r4, r4, r10
 ; P8BE-NEXT:    mtvsrd v2, r5
 ; P8BE-NEXT:    sldi r5, r7, 48
 ; P8BE-NEXT:    sldi r3, r3, 48
@@ -234,47 +234,47 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r4, r5
-; P9LE-NEXT:    subf r4, r5, r4
+; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -291,36 +291,36 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P9BE-NEXT:    ori r4, r4, 8969
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
-; P9BE-NEXT:    subf r6, r5, r3
+; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
-; P9BE-NEXT:    subf r6, r5, r3
+; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r4
-; P9BE-NEXT:    subf r6, r5, r3
+; P9BE-NEXT:    sub r6, r3, r5
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r5, r6, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r5, r5, 95
-; P9BE-NEXT:    subf r3, r5, r3
+; P9BE-NEXT:    sub r3, r3, r5
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -328,12 +328,12 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    vmrghh v2, v2, v4
@@ -359,12 +359,12 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P8LE-NEXT:    mulhwu r12, r9, r3
 ; P8LE-NEXT:    mulhwu r30, r11, r3
 ; P8LE-NEXT:    mulhwu r3, r0, r3
-; P8LE-NEXT:    subf r8, r10, r8
+; P8LE-NEXT:    sub r8, r8, r10
 ; P8LE-NEXT:    srwi r8, r8, 1
-; P8LE-NEXT:    subf r9, r12, r9
+; P8LE-NEXT:    sub r9, r9, r12
 ; P8LE-NEXT:    add r8, r8, r10
-; P8LE-NEXT:    subf r10, r30, r11
+; P8LE-NEXT:    sub r10, r11, r30
-; P8LE-NEXT:    subf r11, r3, r0
+; P8LE-NEXT:    sub r11, r0, r3
 ; P8LE-NEXT:    srwi r9, r9, 1
 ; P8LE-NEXT:    srwi r10, r10, 1
 ; P8LE-NEXT:    srwi r11, r11, 1
@@ -380,11 +380,11 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P8LE-NEXT:    mulli r9, r9, 95
 ; P8LE-NEXT:    mulli r10, r10, 95
 ; P8LE-NEXT:    mulli r3, r3, 95
-; P8LE-NEXT:    subf r5, r8, r5
+; P8LE-NEXT:    sub r5, r5, r8
-; P8LE-NEXT:    subf r6, r9, r6
+; P8LE-NEXT:    sub r6, r6, r9
 ; P8LE-NEXT:    mtfprd f0, r5
-; P8LE-NEXT:    subf r5, r10, r7
+; P8LE-NEXT:    sub r5, r7, r10
-; P8LE-NEXT:    subf r3, r3, r4
+; P8LE-NEXT:    sub r3, r4, r3
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f2, r5
 ; P8LE-NEXT:    xxswapd v2, vs0
@@ -414,14 +414,14 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P8BE-NEXT:    clrlwi r4, r4, 16
 ; P8BE-NEXT:    mulhwu r10, r7, r3
 ; P8BE-NEXT:    mulhwu r3, r4, r3
-; P8BE-NEXT:    subf r11, r8, r5
+; P8BE-NEXT:    sub r11, r5, r8
-; P8BE-NEXT:    subf r12, r9, r6
+; P8BE-NEXT:    sub r12, r6, r9
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    add r8, r11, r8
-; P8BE-NEXT:    subf r11, r10, r7
+; P8BE-NEXT:    sub r11, r7, r10
 ; P8BE-NEXT:    srwi r12, r12, 1
 ; P8BE-NEXT:    add r9, r12, r9
-; P8BE-NEXT:    subf r12, r3, r4
+; P8BE-NEXT:    sub r12, r4, r3
 ; P8BE-NEXT:    srwi r11, r11, 1
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    add r10, r11, r10
@@ -434,10 +434,10 @@ define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
 ; P8BE-NEXT:    mulli r9, r9, 95
 ; P8BE-NEXT:    mulli r10, r10, 95
 ; P8BE-NEXT:    mulli r3, r3, 95
-; P8BE-NEXT:    subf r5, r8, r5
+; P8BE-NEXT:    sub r5, r5, r8
-; P8BE-NEXT:    subf r6, r9, r6
+; P8BE-NEXT:    sub r6, r6, r9
-; P8BE-NEXT:    subf r7, r10, r7
+; P8BE-NEXT:    sub r7, r7, r10
-; P8BE-NEXT:    subf r3, r3, r4
+; P8BE-NEXT:    sub r3, r4, r3
 ; P8BE-NEXT:    sldi r5, r5, 48
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    sldi r4, r7, 48
@@ -465,47 +465,47 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 8969
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r6, r4, r5
-; P9LE-NEXT:    subf r4, r6, r4
+; P9LE-NEXT:    sub r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r6
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r6, r4, 95
-; P9LE-NEXT:    subf r3, r6, r3
+; P9LE-NEXT:    sub r3, r3, r6
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r6, r3, 16
 ; P9LE-NEXT:    mulhwu r7, r6, r5
-; P9LE-NEXT:    subf r6, r7, r6
+; P9LE-NEXT:    sub r6, r6, r7
 ; P9LE-NEXT:    srwi r6, r6, 1
 ; P9LE-NEXT:    add r6, r6, r7
 ; P9LE-NEXT:    srwi r6, r6, 6
 ; P9LE-NEXT:    mulli r7, r6, 95
-; P9LE-NEXT:    subf r3, r7, r3
+; P9LE-NEXT:    sub r3, r3, r7
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r7, r3, 16
 ; P9LE-NEXT:    mulhwu r8, r7, r5
-; P9LE-NEXT:    subf r7, r8, r7
+; P9LE-NEXT:    sub r7, r7, r8
 ; P9LE-NEXT:    srwi r7, r7, 1
 ; P9LE-NEXT:    add r7, r7, r8
 ; P9LE-NEXT:    srwi r7, r7, 6
 ; P9LE-NEXT:    mulli r8, r7, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
 ; P9LE-NEXT:    clrlwi r8, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r8, r5
-; P9LE-NEXT:    subf r8, r5, r8
+; P9LE-NEXT:    sub r8, r8, r5
 ; P9LE-NEXT:    srwi r8, r8, 1
 ; P9LE-NEXT:    add r5, r8, r5
 ; P9LE-NEXT:    srwi r5, r5, 6
 ; P9LE-NEXT:    mulli r8, r5, 95
-; P9LE-NEXT:    subf r3, r8, r3
+; P9LE-NEXT:    sub r3, r3, r8
 ; P9LE-NEXT:    vmrglh v3, v4, v3
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
@@ -534,36 +534,36 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P9BE-NEXT:    ori r5, r5, 8969
 ; P9BE-NEXT:    clrlwi r4, r3, 16
 ; P9BE-NEXT:    mulhwu r6, r4, r5
-; P9BE-NEXT:    subf r4, r6, r4
+; P9BE-NEXT:    sub r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 1
 ; P9BE-NEXT:    add r4, r4, r6
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r6, r4, 95
-; P9BE-NEXT:    subf r3, r6, r3
+; P9BE-NEXT:    sub r3, r3, r6
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
 ; P9BE-NEXT:    li r3, 4
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r6, r3, 16
 ; P9BE-NEXT:    mulhwu r7, r6, r5
-; P9BE-NEXT:    subf r6, r7, r6
+; P9BE-NEXT:    sub r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 1
 ; P9BE-NEXT:    add r6, r6, r7
 ; P9BE-NEXT:    srwi r6, r6, 6
 ; P9BE-NEXT:    mulli r7, r6, 95
-; P9BE-NEXT:    subf r3, r7, r3
+; P9BE-NEXT:    sub r3, r3, r7
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r7, r3, 16
 ; P9BE-NEXT:    mulhwu r8, r7, r5
-; P9BE-NEXT:    subf r7, r8, r7
+; P9BE-NEXT:    sub r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 1
 ; P9BE-NEXT:    add r7, r7, r8
 ; P9BE-NEXT:    srwi r7, r7, 6
 ; P9BE-NEXT:    mulli r8, r7, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    mtvsrd v4, r3
@@ -571,12 +571,12 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P9BE-NEXT:    vextuhlx r3, r3, v2
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r5, r3, r5
-; P9BE-NEXT:    subf r8, r5, r3
+; P9BE-NEXT:    sub r8, r3, r5
 ; P9BE-NEXT:    srwi r8, r8, 1
 ; P9BE-NEXT:    add r5, r8, r5
 ; P9BE-NEXT:    srwi r5, r5, 6
 ; P9BE-NEXT:    mulli r8, r5, 95
-; P9BE-NEXT:    subf r3, r8, r3
+; P9BE-NEXT:    sub r3, r3, r8
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    sldi r3, r4, 48
@@ -614,14 +614,14 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P8LE-NEXT:    mulhwu r0, r11, r4
 ; P8LE-NEXT:    clrlwi r30, r5, 16
 ; P8LE-NEXT:    mulhwu r4, r30, r4
-; P8LE-NEXT:    subf r8, r10, r8
+; P8LE-NEXT:    sub r8, r8, r10
 ; P8LE-NEXT:    srwi r8, r8, 1
-; P8LE-NEXT:    subf r9, r12, r9
+; P8LE-NEXT:    sub r9, r9, r12
 ; P8LE-NEXT:    add r8, r8, r10
-; P8LE-NEXT:    subf r10, r0, r11
+; P8LE-NEXT:    sub r10, r11, r0
 ; P8LE-NEXT:    srwi r9, r9, 1
 ; P8LE-NEXT:    srwi r10, r10, 1
-; P8LE-NEXT:    subf r11, r4, r30
+; P8LE-NEXT:    sub r11, r30, r4
 ; P8LE-NEXT:    add r9, r9, r12
 ; P8LE-NEXT:    srwi r8, r8, 6
 ; P8LE-NEXT:    ld r30, -16(r1) # 8-byte Folded Reload
@@ -642,13 +642,13 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P8LE-NEXT:    mulli r4, r4, 95
 ; P8LE-NEXT:    xxswapd v3, vs1
 ; P8LE-NEXT:    xxswapd v1, vs2
-; P8LE-NEXT:    subf r3, r12, r3
+; P8LE-NEXT:    sub r3, r3, r12
 ; P8LE-NEXT:    xxswapd v6, vs3
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r9, r7
+; P8LE-NEXT:    sub r3, r7, r9
-; P8LE-NEXT:    subf r6, r8, r6
+; P8LE-NEXT:    sub r6, r6, r8
 ; P8LE-NEXT:    mtfprd f4, r3
-; P8LE-NEXT:    subf r3, r4, r5
+; P8LE-NEXT:    sub r3, r5, r4
 ; P8LE-NEXT:    mtfprd f1, r6
 ; P8LE-NEXT:    mtfprd f5, r3
 ; P8LE-NEXT:    xxswapd v5, vs4
@@ -681,13 +681,13 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    mulhwu r0, r11, r4
 ; P8BE-NEXT:    mulhwu r4, r5, r4
-; P8BE-NEXT:    subf r8, r10, r8
+; P8BE-NEXT:    sub r8, r8, r10
-; P8BE-NEXT:    subf r9, r12, r9
+; P8BE-NEXT:    sub r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 1
 ; P8BE-NEXT:    add r8, r8, r10
-; P8BE-NEXT:    subf r10, r0, r11
+; P8BE-NEXT:    sub r10, r11, r0
 ; P8BE-NEXT:    srwi r9, r9, 1
-; P8BE-NEXT:    subf r11, r4, r5
+; P8BE-NEXT:    sub r11, r5, r4
 ; P8BE-NEXT:    add r9, r9, r12
 ; P8BE-NEXT:    srwi r8, r8, 6
 ; P8BE-NEXT:    srwi r11, r11, 1
@@ -705,15 +705,15 @@ define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
 ; P8BE-NEXT:    mulli r9, r4, 95
 ; P8BE-NEXT:    mtvsrd v2, r8
 ; P8BE-NEXT:    mulli r8, r10, 95
-; P8BE-NEXT:    subf r3, r12, r3
+; P8BE-NEXT:    sub r3, r3, r12
-; P8BE-NEXT:    subf r6, r11, r6
+; P8BE-NEXT:    sub r6, r6, r11
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r6, r6, 48
 ; P8BE-NEXT:    sldi r10, r10, 48
 ; P8BE-NEXT:    mtvsrd v3, r3
-; P8BE-NEXT:    subf r3, r9, r5
+; P8BE-NEXT:    sub r3, r5, r9
-; P8BE-NEXT:    subf r7, r8, r7
+; P8BE-NEXT:    sub r7, r7, r8
 ; P8BE-NEXT:    mtvsrd v5, r6
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    sldi r5, r7, 48
@@ -755,12 +755,12 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    clrlwi r4, r3, 16
 ; P9LE-NEXT:    mulhwu r5, r4, r5
-; P9LE-NEXT:    subf r4, r5, r4
+; P9LE-NEXT:    sub r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 1
 ; P9LE-NEXT:    add r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 6
 ; P9LE-NEXT:    mulli r4, r4, 95
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 4
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -792,12 +792,12 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P9BE-NEXT:    vmrghh v3, v4, v3
 ; P9BE-NEXT:    clrlwi r3, r3, 16
 ; P9BE-NEXT:    mulhwu r4, r3, r4
-; P9BE-NEXT:    subf r5, r4, r3
+; P9BE-NEXT:    sub r5, r3, r4
 ; P9BE-NEXT:    srwi r5, r5, 1
 ; P9BE-NEXT:    add r4, r5, r4
 ; P9BE-NEXT:    srwi r4, r4, 6
 ; P9BE-NEXT:    mulli r4, r4, 95
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 4
@@ -819,7 +819,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P8LE-NEXT:    rldicl r7, r4, 48, 48
 ; P8LE-NEXT:    clrlwi r6, r5, 16
 ; P8LE-NEXT:    mulhwu r3, r6, r3
-; P8LE-NEXT:    subf r6, r3, r6
+; P8LE-NEXT:    sub r6, r6, r3
 ; P8LE-NEXT:    srwi r6, r6, 1
 ; P8LE-NEXT:    add r3, r6, r3
 ; P8LE-NEXT:    clrldi r6, r4, 48
@@ -834,7 +834,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P8LE-NEXT:    mtfprd f3, r4
 ; P8LE-NEXT:    xxswapd v2, vs0
 ; P8LE-NEXT:    xxswapd v3, vs1
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
 ; P8LE-NEXT:    xxswapd v5, vs3
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    vmrglh v2, v3, v2
@@ -853,7 +853,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P8BE-NEXT:    clrlwi r5, r5, 16
 ; P8BE-NEXT:    clrlwi r7, r7, 26
 ; P8BE-NEXT:    mulhwu r3, r5, r3
-; P8BE-NEXT:    subf r6, r3, r5
+; P8BE-NEXT:    sub r6, r5, r3
 ; P8BE-NEXT:    srwi r6, r6, 1
 ; P8BE-NEXT:    add r3, r6, r3
 ; P8BE-NEXT:    rldicl r6, r4, 32, 48
@@ -868,7 +868,7 @@ define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
 ; P8BE-NEXT:    sldi r4, r4, 48
 ; P8BE-NEXT:    mtvsrd v3, r6
 ; P8BE-NEXT:    mtvsrd v5, r4
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    vmrghh v2, v3, v2
 ; P8BE-NEXT:    sldi r3, r3, 48
 ; P8BE-NEXT:    mtvsrd v4, r3
@@ -893,7 +893,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 47143
 ; P9LE-NEXT:    srwi r4, r4, 4
 ; P9LE-NEXT:    mulli r4, r4, 23
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 6
 ; P9LE-NEXT:    vextuhrx r3, r3, v2
@@ -903,7 +903,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9LE-NEXT:    ori r5, r5, 30865
 ; P9LE-NEXT:    srwi r4, r4, 11
 ; P9LE-NEXT:    mulli r4, r4, 5423
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v3, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    li r3, 2
@@ -912,7 +912,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9LE-NEXT:    mulhwu r4, r4, r5
 ; P9LE-NEXT:    srwi r4, r4, 8
 ; P9LE-NEXT:    mulli r4, r4, 654
-; P9LE-NEXT:    subf r3, r4, r3
+; P9LE-NEXT:    sub r3, r3, r4
 ; P9LE-NEXT:    xxswapd v4, vs0
 ; P9LE-NEXT:    mtfprd f0, r3
 ; P9LE-NEXT:    xxswapd v2, vs0
@@ -932,7 +932,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 11
 ; P9BE-NEXT:    mulli r4, r4, 5423
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    lis r4, -19946
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v3, r3
@@ -943,7 +943,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9BE-NEXT:    mulhwu r4, r3, r4
 ; P9BE-NEXT:    srwi r4, r4, 4
 ; P9BE-NEXT:    mulli r4, r4, 23
-; P9BE-NEXT:    subf r3, r4, r3
+; P9BE-NEXT:    sub r3, r3, r4
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v4, r3
 ; P9BE-NEXT:    li r3, 2
@@ -956,7 +956,7 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P9BE-NEXT:    mulhwu r3, r3, r5
 ; P9BE-NEXT:    srwi r3, r3, 8
 ; P9BE-NEXT:    mulli r3, r3, 654
-; P9BE-NEXT:    subf r3, r3, r4
+; P9BE-NEXT:    sub r3, r4, r3
 ; P9BE-NEXT:    sldi r3, r3, 48
 ; P9BE-NEXT:    mtvsrd v2, r3
 ; P9BE-NEXT:    li r3, 0
@@ -992,10 +992,10 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P8LE-NEXT:    srwi r8, r8, 8
 ; P8LE-NEXT:    mulli r7, r7, 5423
 ; P8LE-NEXT:    mulli r8, r8, 654
-; P8LE-NEXT:    subf r3, r3, r5
+; P8LE-NEXT:    sub r3, r5, r3
-; P8LE-NEXT:    subf r5, r7, r6
+; P8LE-NEXT:    sub r5, r6, r7
 ; P8LE-NEXT:    mtfprd f0, r3
-; P8LE-NEXT:    subf r3, r8, r4
+; P8LE-NEXT:    sub r3, r4, r8
 ; P8LE-NEXT:    mtfprd f1, r5
 ; P8LE-NEXT:    mtfprd f2, r3
 ; P8LE-NEXT:    xxswapd v2, vs0
@@ -1032,12 +1032,12 @@ define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
 ; P8BE-NEXT:    srwi r8, r8, 8
 ; P8BE-NEXT:    mulli r7, r7, 23
 ; P8BE-NEXT:    mulli r8, r8, 654
-; P8BE-NEXT:    subf r3, r3, r5
+; P8BE-NEXT:    sub r3, r5, r3
 ; P8BE-NEXT:    sldi r5, r9, 48
 ; P8BE-NEXT:    mtvsrd v2, r5
-; P8BE-NEXT:    subf r5, r7, r6
+; P8BE-NEXT:    sub r5, r6, r7
 ; P8BE-NEXT:    sldi r3, r3, 48
-; P8BE-NEXT:    subf r4, r8, r4
+; P8BE-NEXT:    sub r4, r4, r8
 ; P8BE-NEXT:    sldi r5, r5, 48
 ; P8BE-NEXT:    mtvsrd v3, r3
 ; P8BE-NEXT:    sldi r3, r4, 48

test/CodeGen/PowerPC/use-cr-result-of-dom-icmp-st.ll

@@ -25,7 +25,7 @@ define i64 @ll_a_op_b__2(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB0_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -54,7 +54,7 @@ define i64 @ll_a_op_b__1(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB1_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -82,7 +82,7 @@ define i64 @ll_a_op_b_0(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB2_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -111,7 +111,7 @@ define i64 @ll_a_op_b_1(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB3_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -140,7 +140,7 @@ define i64 @ll_a_op_b_2(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB4_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -168,7 +168,7 @@ define i64 @ll_a__2(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB5_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -195,7 +195,7 @@ define i64 @ll_a__1(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB6_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -222,7 +222,7 @@ define i64 @ll_a_0(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB7_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -249,7 +249,7 @@ define i64 @ll_a_1(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB8_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -276,7 +276,7 @@ define i64 @ll_a_2(i64 %a, i64 %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB9_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mulld r3, r4, r3
 ; CHECK-NEXT:    blr
 entry:
@@ -301,7 +301,7 @@ define i64 @i_a_op_b__2(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    bgt cr0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB10_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
@@ -334,7 +334,7 @@ define i64 @i_a_op_b__1(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB11_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
@@ -366,7 +366,7 @@ define i64 @i_a_op_b_0(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB12_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
@@ -395,7 +395,7 @@ define i64 @i_a_op_b_1(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    bgt cr0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB13_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
@@ -425,7 +425,7 @@ define i64 @i_a_op_b_2(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    bgt cr0, .LBB14_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB14_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
@@ -454,7 +454,7 @@ define i64 @i_a__2(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    bgt cr0, .LBB15_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB15_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
@@ -485,7 +485,7 @@ define i64 @i_a__1(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB16_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
@@ -515,7 +515,7 @@ define i64 @i_a_0(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    blr
 ; CHECK-NEXT:  .LBB17_2: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:    extsw r3, r4
 ; CHECK-NEXT:    blr
@@ -542,7 +542,7 @@ define i64 @i_a_1(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    bgt cr0, .LBB18_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB18_2: # %return
 ; CHECK-NEXT:    extsw r3, r4
@@ -570,7 +570,7 @@ define i64 @i_a_2(i32 signext %a, i32 signext %b) {
 ; CHECK-NEXT:    bgt cr0, .LBB19_2
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    li r5, 1
-; CHECK-NEXT:    isel r4, r5, r4, lt
+; CHECK-NEXT:    isellt r4, r5, r4
 ; CHECK-NEXT:    mullw r4, r4, r3
 ; CHECK-NEXT:  .LBB19_2: # %return
 ; CHECK-NEXT:    extsw r3, r4

test/CodeGen/PowerPC/vec-min-max.ll

@@ -71,11 +71,11 @@ define <2 x i64> @getsmaxi64(<2 x i64> %a, <2 x i64> %b) {
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
-; NOP8VEC-NEXT:    isel 5, 4, 3, 1
+; NOP8VEC-NEXT:    iselgt 5, 4, 3
 ; NOP8VEC-NEXT:    std 5, -8(1)
 ; NOP8VEC-NEXT:    ld 5, -32(1)
 ; NOP8VEC-NEXT:    cmpd 6, 5
-; NOP8VEC-NEXT:    isel 3, 4, 3, 1
+; NOP8VEC-NEXT:    iselgt 3, 4, 3
 ; NOP8VEC-NEXT:    std 3, -16(1)
 ; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    lxvd2x 0, 0, 3
@@ -188,11 +188,11 @@ define <2 x i64> @getsmini64(<2 x i64> %a, <2 x i64> %b) {
 ; NOP8VEC-NEXT:    cmpd 4, 3
 ; NOP8VEC-NEXT:    li 3, 0
 ; NOP8VEC-NEXT:    li 4, -1
-; NOP8VEC-NEXT:    isel 5, 4, 3, 0
+; NOP8VEC-NEXT:    isellt 5, 4, 3
 ; NOP8VEC-NEXT:    std 5, -8(1)
 ; NOP8VEC-NEXT:    ld 5, -32(1)
 ; NOP8VEC-NEXT:    cmpd 6, 5
-; NOP8VEC-NEXT:    isel 3, 4, 3, 0
+; NOP8VEC-NEXT:    isellt 3, 4, 3
 ; NOP8VEC-NEXT:    std 3, -16(1)
 ; NOP8VEC-NEXT:    addi 3, 1, -16
 ; NOP8VEC-NEXT:    lxvd2x 0, 0, 3

test/CodeGen/PowerPC/vsx.ll

@@ -2146,11 +2146,11 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-NEXT:    cmpld r4, r3
 ; CHECK-NEXT:    li r3, 0
 ; CHECK-NEXT:    li r4, -1
-; CHECK-NEXT:    isel r5, r4, r3, lt
+; CHECK-NEXT:    isellt r5, r4, r3
 ; CHECK-NEXT:    std r5, -8(r1)
 ; CHECK-NEXT:    ld r5, -32(r1)
 ; CHECK-NEXT:    cmpld r6, r5
-; CHECK-NEXT:    isel r3, r4, r3, lt
+; CHECK-NEXT:    isellt r3, r4, r3
 ; CHECK-NEXT:    std r3, -16(r1)
 ; CHECK-NEXT:    addi r3, r1, -16
 ; CHECK-NEXT:    lxvd2x v2, 0, r3
@@ -2168,11 +2168,11 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-REG-NEXT:    cmpld r4, r3
 ; CHECK-REG-NEXT:    li r3, 0
 ; CHECK-REG-NEXT:    li r4, -1
-; CHECK-REG-NEXT:    isel r5, r4, r3, lt
+; CHECK-REG-NEXT:    isellt r5, r4, r3
 ; CHECK-REG-NEXT:    std r5, -8(r1)
 ; CHECK-REG-NEXT:    ld r5, -32(r1)
 ; CHECK-REG-NEXT:    cmpld r6, r5
-; CHECK-REG-NEXT:    isel r3, r4, r3, lt
+; CHECK-REG-NEXT:    isellt r3, r4, r3
 ; CHECK-REG-NEXT:    std r3, -16(r1)
 ; CHECK-REG-NEXT:    addi r3, r1, -16
 ; CHECK-REG-NEXT:    lxvd2x v2, 0, r3
@@ -2189,12 +2189,12 @@ define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK-FISL-NEXT:    cmpld r4, r3
 ; CHECK-FISL-NEXT:    li r3, 0
 ; CHECK-FISL-NEXT:    li r4, -1
-; CHECK-FISL-NEXT:    isel r5, r4, r3, lt
+; CHECK-FISL-NEXT:    isellt r5, r4, r3
 ; CHECK-FISL-NEXT:    std r5, -8(r1)
 ; CHECK-FISL-NEXT:    ld r5, -32(r1)
 ; CHECK-FISL-NEXT:    ld r6, -48(r1)
 ; CHECK-FISL-NEXT:    cmpld r6, r5
-; CHECK-FISL-NEXT:    isel r3, r4, r3, lt
+; CHECK-FISL-NEXT:    isellt r3, r4, r3
 ; CHECK-FISL-NEXT:    std r3, -16(r1)
 ; CHECK-FISL-NEXT:    addi r3, r1, -16
 ; CHECK-FISL-NEXT:    lxvd2x vs0, 0, r3

test/MC/Disassembler/PowerPC/ppc64-encoding-ext.txt

@@ -1825,16 +1825,16 @@
 # CHECK: addic. 2, 3, -128
 0x34 0x43 0xff 0x80
 
-# CHECK: subf 2, 4, 3
+# CHECK: sub 2, 3, 4
 0x7c 0x44 0x18 0x50
 
-# CHECK: subf. 2, 4, 3
+# CHECK: sub. 2, 3, 4
 0x7c 0x44 0x18 0x51
 
-# CHECK: subfc 2, 4, 3
+# CHECK: subc 2, 3, 4
 0x7c 0x44 0x18 0x10
 
-# CHECK: subfc. 2, 4, 3
+# CHECK: subc. 2, 3, 4
 0x7c 0x44 0x18 0x11
 
 # CHECK: cmpdi 2, 3, 128
@@ -2239,16 +2239,16 @@
 # CHECK: mr 2, 3
 0x7c 0x62 0x1b 0x78
 
-# CHECK: or. 2, 3, 3
+# CHECK: mr. 2, 3
 0x7c 0x62 0x1b 0x79
 
-# CHECK: nor 2, 3, 3
+# CHECK: not 2, 3
 0x7c 0x62 0x18 0xf8
 
-# CHECK: nor. 2, 3, 3
+# CHECK: not. 2, 3
 0x7c 0x62 0x18 0xf9
 
-# CHECK: mtcrf 255, 2
+# CHECK: mtcr 2
 0x7c 0x4f 0xf1 0x20
 
 # CHECK: dss 3

test/MC/Disassembler/PowerPC/ppc64-encoding-p8htm.txt

@@ -6,10 +6,10 @@
 # CHECK: tbegin. 0
 0x7c 0x00 0x05 0x1d
 
-# CHECK: tend. 0
+# CHECK: tend.
 0x7c 0x00 0x05 0x5d
 
-# CHECK: tend. 1
+# CHECK: tendall.
 0x7e 0x00 0x05 0x5d
 
 # CHECK: tabort. 3
@@ -27,10 +27,10 @@
 # CHECK: tabortwci. 0, 4, 2
 0x7c 0x04 0x16 0x9d
 
-# CHECK: tsr. 1
+# CHECK: tresume.
 0x7c 0x20 0x05 0xdd
 
-# CHECK: tsr. 0
+# CHECK: tsuspend.
 0x7c 0x00 0x05 0xdd
 
 # CHECK: tcheck 0

test/MC/Disassembler/PowerPC/ppc64-encoding.txt

@@ -79,7 +79,7 @@
 # CHECK: mfbhrbe 9, 983
 0x7d 0x3e 0xba 0x5c
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x4c 0x00 0x09 0x24
 
 # CHECK: lbz 2, 128(4)                   
@@ -244,10 +244,10 @@
 # CHECK: addo. 2, 3, 4
 0x7c 0x43 0x26 0x15
 
-# CHECK: subf 2, 3, 4                    
+# CHECK: sub 2, 4, 3                     
 0x7c 0x43 0x20 0x50
 
-# CHECK: subf. 2, 3, 4                   
+# CHECK: sub. 2, 4, 3                    
 0x7c 0x43 0x20 0x51
 
 # CHECK: subfo 2, 3, 4
@@ -277,11 +277,11 @@
 # CHECK: addco. 2, 3, 4
 0x7c 0x43 0x24 0x15
 
-# CHECK: subfc 2, 3, 4                   
+# CHECK: subc 2, 4, 3                    
 0x7c 0x43 0x20 0x10
 
-# CHECK: subfc 2, 3, 4                   
+# CHECK: subc. 2, 4, 3                   
-0x7c 0x43 0x20 0x10
+0x7c 0x43 0x20 0x11
 
 # CHECK: subfco 2, 3, 4
 0x7c 0x43 0x24 0x10

test/MC/Disassembler/PowerPC/ppc64le-encoding.txt

@@ -79,7 +79,7 @@
 # CHECK: mfbhrbe 9, 983
 0x5c 0xba 0x3e 0x7d
 
-# CHECK: rfebb 1
+# CHECK: rfebb
 0x24 0x09 0x00 0x4c
 
 # CHECK: lbz 2, 128(4)
@@ -241,10 +241,10 @@
 # CHECK: addo. 2, 3, 4
 0x15 0x26 0x43 0x7c
 
-# CHECK: subf 2, 3, 4
+# CHECK: sub 2, 4, 3
 0x50 0x20 0x43 0x7c
 
-# CHECK: subf. 2, 3, 4
+# CHECK: sub. 2, 4, 3
 0x51 0x20 0x43 0x7c
 
 # CHECK: subfo 2, 3, 4
@@ -274,11 +274,11 @@
 # CHECK: addco. 2, 3, 4
 0x15 0x24 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
+# CHECK: subc 2, 4, 3
 0x10 0x20 0x43 0x7c
 
-# CHECK: subfc 2, 3, 4
+# CHECK: subc. 2, 4, 3
-0x10 0x20 0x43 0x7c
+0x11 0x20 0x43 0x7c
 
 # CHECK: subfco 2, 3, 4
 0x10 0x24 0x43 0x7c

test/MC/PowerPC/htm.s

@@ -8,11 +8,11 @@
 # CHECK-LE: tbegin. 1                      # encoding: [0x1d,0x05,0x20,0x7c]
             tbegin. 1
 
-# CHECK-BE: tend. 0                        # encoding: [0x7c,0x00,0x05,0x5d]
+# CHECK-BE: tend.                          # encoding: [0x7c,0x00,0x05,0x5d]
-# CHECK-LE: tend. 0                        # encoding: [0x5d,0x05,0x00,0x7c]
+# CHECK-LE: tend.                          # encoding: [0x5d,0x05,0x00,0x7c]
             tend. 0
-# CHECK-BE: tend. 1                        # encoding: [0x7e,0x00,0x05,0x5d]
+# CHECK-BE: tendall.                       # encoding: [0x7e,0x00,0x05,0x5d]
-# CHECK-LE: tend. 1                        # encoding: [0x5d,0x05,0x00,0x7e]
+# CHECK-LE: tendall.                       # encoding: [0x5d,0x05,0x00,0x7e]
             tend. 1
 
 # CHECK-BE: tabort. 9                      # encoding: [0x7c,0x09,0x07,0x1d]
@@ -31,11 +31,11 @@
 # CHECK-LE: tabortwci. 0, 9, 0             # encoding: [0x9d,0x06,0x09,0x7c]
             tabortwci. 0, 9, 0
 
-# CHECK-BE: tsr. 0                         # encoding: [0x7c,0x00,0x05,0xdd]
+# CHECK-BE: tsuspend.                      # encoding: [0x7c,0x00,0x05,0xdd]
-# CHECK-LE: tsr. 0                         # encoding: [0xdd,0x05,0x00,0x7c]
+# CHECK-LE: tsuspend.                      # encoding: [0xdd,0x05,0x00,0x7c]
             tsr. 0
-# CHECK-BE: tsr. 1                         # encoding: [0x7c,0x20,0x05,0xdd]
+# CHECK-BE: tresume.                       # encoding: [0x7c,0x20,0x05,0xdd]
-# CHECK-LE: tsr. 1                         # encoding: [0xdd,0x05,0x20,0x7c]
+# CHECK-LE: tresume.                       # encoding: [0xdd,0x05,0x20,0x7c]
             tsr. 1
 
 # CHECK-BE: tcheck 0                       # encoding: [0x7c,0x00,0x05,0x9c]

test/MC/PowerPC/ppc64-encoding.s

@@ -161,8 +161,8 @@
 # CHECK-BE: mfbhrbe 9, 983                  # encoding: [0x7d,0x3e,0xba,0x5c]
 # CHECK-LE: mfbhrbe 9, 983                  # encoding: [0x5c,0xba,0x3e,0x7d]
             mfbhrbe 9, 983
-# CHECK-BE: rfebb 1                         # encoding: [0x4c,0x00,0x09,0x24]
+# CHECK-BE: rfebb                           # encoding: [0x4c,0x00,0x09,0x24]
-# CHECK-LE: rfebb 1                         # encoding: [0x24,0x09,0x00,0x4c]
+# CHECK-LE: rfebb                           # encoding: [0x24,0x09,0x00,0x4c]
             rfebb 1
 
 # Fixed-point facility
@@ -345,11 +345,11 @@
 # CHECK-BE: addo. 2, 3, 4                   # encoding: [0x7c,0x43,0x26,0x15]
 # CHECK-LE: addo. 2, 3, 4                   # encoding: [0x15,0x26,0x43,0x7c]
             addo. 2, 3, 4
-# CHECK-BE: subf 2, 3, 4                    # encoding: [0x7c,0x43,0x20,0x50]
+# CHECK-BE: sub 2, 4, 3                     # encoding: [0x7c,0x43,0x20,0x50]
-# CHECK-LE: subf 2, 3, 4                    # encoding: [0x50,0x20,0x43,0x7c]
+# CHECK-LE: sub 2, 4, 3                     # encoding: [0x50,0x20,0x43,0x7c]
             subf 2, 3, 4
-# CHECK-BE: subf. 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x51]
+# CHECK-BE: sub. 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x51]
-# CHECK-LE: subf. 2, 3, 4                   # encoding: [0x51,0x20,0x43,0x7c]
+# CHECK-LE: sub. 2, 4, 3                    # encoding: [0x51,0x20,0x43,0x7c]
             subf. 2, 3, 4
 # CHECK-BE: subfo 2, 3, 4                   # encoding: [0x7c,0x43,0x24,0x50]
 # CHECK-LE: subfo 2, 3, 4                   # encoding: [0x50,0x24,0x43,0x7c]
@@ -379,11 +379,11 @@
 # CHECK-BE: addco. 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x15]
 # CHECK-LE: addco. 2, 3, 4                  # encoding: [0x15,0x24,0x43,0x7c]
             addco. 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
-# CHECK-BE: subfc 2, 3, 4                   # encoding: [0x7c,0x43,0x20,0x10]
+# CHECK-BE: subc 2, 4, 3                    # encoding: [0x7c,0x43,0x20,0x10]
-# CHECK-LE: subfc 2, 3, 4                   # encoding: [0x10,0x20,0x43,0x7c]
+# CHECK-LE: subc 2, 4, 3                    # encoding: [0x10,0x20,0x43,0x7c]
             subfc 2, 3, 4
 # CHECK-BE: subfco 2, 3, 4                  # encoding: [0x7c,0x43,0x24,0x10]
 # CHECK-LE: subfco 2, 3, 4                  # encoding: [0x10,0x24,0x43,0x7c]

test/MC/PowerPC/ppc64-operands.s

@@ -20,12 +20,12 @@
 # CHECK-LE: add 31, 31, 31                  # encoding: [0x14,0xfa,0xff,0x7f]
             add 31, 31, 31
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, 0, 0
 
-# CHECK-BE: addi 1, 0, 0                    # encoding: [0x38,0x20,0x00,0x00]
+# CHECK-BE: li 1, 0                         # encoding: [0x38,0x20,0x00,0x00]
-# CHECK-LE: addi 1, 0, 0                    # encoding: [0x00,0x00,0x20,0x38]
+# CHECK-LE: li 1, 0                         # encoding: [0x00,0x00,0x20,0x38]
             addi 1, %r0, 0
 
 # Signed 16-bit immediate operands
@@ -34,12 +34,12 @@
 # CHECK-LE: addi 1, 2, 0                    # encoding: [0x00,0x00,0x22,0x38]
             addi 1, 2, 0
 
-# CHECK-BE: addi 1, 0, -32768               # encoding: [0x38,0x20,0x80,0x00]
+# CHECK-BE: li 1, -32768                    # encoding: [0x38,0x20,0x80,0x00]
-# CHECK-LE: addi 1, 0, -32768               # encoding: [0x00,0x80,0x20,0x38]
+# CHECK-LE: li 1, -32768                    # encoding: [0x00,0x80,0x20,0x38]
             addi 1, 0, -32768
 
-# CHECK-BE: addi 1, 0, 32767                # encoding: [0x38,0x20,0x7f,0xff]
+# CHECK-BE: li 1, 32767                     # encoding: [0x38,0x20,0x7f,0xff]
-# CHECK-LE: addi 1, 0, 32767                # encoding: [0xff,0x7f,0x20,0x38]
+# CHECK-LE: li 1, 32767                     # encoding: [0xff,0x7f,0x20,0x38]
             addi 1, 0, 32767
 
 # Unsigned 16-bit immediate operands
@@ -54,12 +54,12 @@
 
 # Signed 16-bit immediate operands (extended range for addis)
 
-# CHECK-BE: addis 1, 0, 0                   # encoding: [0x3c,0x20,0x00,0x00]
+# CHECK-BE: lis 1, 0                        # encoding: [0x3c,0x20,0x00,0x00]
-# CHECK-LE: addis 1, 0, 0                   # encoding: [0x00,0x00,0x20,0x3c]
+# CHECK-LE: lis 1, 0                        # encoding: [0x00,0x00,0x20,0x3c]
             addis 1, 0, -65536
 
-# CHECK-BE: addis 1, 0, -1                  # encoding: [0x3c,0x20,0xff,0xff]
+# CHECK-BE: lis 1, -1                       # encoding: [0x3c,0x20,0xff,0xff]
-# CHECK-LE: addis 1, 0, -1                  # encoding: [0xff,0xff,0x20,0x3c]
+# CHECK-LE: lis 1, -1                       # encoding: [0xff,0xff,0x20,0x3c]
             addis 1, 0, 65535
 
 # D-Form memory operands