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[PowerPC] Add missing legalization for vector BSWAP
We somehow missed doing this when we were working on Power9 exploitation. This just adds the missing legalization and cost for producing the vector intrinsics. Differential revision: https://reviews.llvm.org/D70436
This commit is contained in:
Nemanja Ivanovic
parent
f7ddeeeea4
commit
900a92f3eb
@ -922,7 +922,10 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::FREM, MVT::f128, Expand);
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}
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setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
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setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
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setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
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setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
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setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);
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}
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if (Subtarget.hasP9Altivec()) {
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@ -2948,19 +2948,25 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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// Vector Byte-Reverse H/W/D/Q Word
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def XXBRH : XX2_XT6_XO5_XB6<60, 7, 475, "xxbrh", vsrc, []>;
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def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, []>;
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def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, []>;
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def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc,
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[(set v4i32:$XT, (bswap v4i32:$XB))]>;
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def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc,
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[(set v2i64:$XT, (bswap v2i64:$XB))]>;
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def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
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// Vector Reverse
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def : Pat<(v8i16 (PPCxxreverse v8i16 :$A)),
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(v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
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def : Pat<(v8i16 (bswap v8i16 :$A)),
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(v8i16 (COPY_TO_REGCLASS (XXBRH (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
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def : Pat<(v4i32 (PPCxxreverse v4i32 :$A)),
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(v4i32 (XXBRW $A))>;
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def : Pat<(v2i64 (PPCxxreverse v2i64 :$A)),
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(v2i64 (XXBRD $A))>;
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def : Pat<(v1i128 (PPCxxreverse v1i128 :$A)),
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(v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
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def : Pat<(v1i128 (bswap v1i128 :$A)),
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(v1i128 (COPY_TO_REGCLASS (XXBRQ (COPY_TO_REGCLASS $A, VSRC)), VRRC))>;
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// Vector Permute
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def XXPERM : XX3_XT5_XA5_XB5<60, 26, "xxperm" , vsrc, vsrc, vsrc,
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@ -943,6 +943,20 @@ int PPCTTIImpl::getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy,
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return Cost;
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}
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unsigned PPCTTIImpl::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF) {
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return BaseT::getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
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}
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unsigned PPCTTIImpl::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Type*> Tys, FastMathFlags FMF,
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unsigned ScalarizationCostPassed) {
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if (ID == Intrinsic::bswap && ST->hasP9Vector())
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return TLI->getTypeLegalizationCost(DL, RetTy).first;
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return BaseT::getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
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ScalarizationCostPassed);
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}
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bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
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LoopInfo *LI, DominatorTree *DT,
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AssumptionCache *AC, TargetLibraryInfo *LibInfo) {
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@ -108,6 +108,11 @@ public:
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unsigned AddressSpace,
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bool UseMaskForCond = false,
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bool UseMaskForGaps = false);
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unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Value*> Args, FastMathFlags FMF, unsigned VF);
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unsigned getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
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ArrayRef<Type*> Tys, FastMathFlags FMF,
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unsigned ScalarizationCostPassed = UINT_MAX);
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/// @}
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};
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115
test/CodeGen/PowerPC/vec-bswap.ll
Normal file
115
test/CodeGen/PowerPC/vec-bswap.ll
Normal file
@ -0,0 +1,115 @@
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \
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; RUN: -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s
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define dso_local void @test(i32* %Arr, i32 signext %Len) {
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; CHECK-LABEL: test:
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; CHECK: lxvx [[REG:vs[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}}
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; CHECK-NEXT: xxbrw vs{{[0-9]+}}, [[REG]]
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entry:
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%cmp1 = icmp slt i32 0, %Len
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br i1 %cmp1, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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%min.iters.check = icmp ult i32 %Len, 4
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br i1 %min.iters.check, label %scalar.ph, label %vector.ph
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vector.ph: ; preds = %for.body.lr.ph
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%n.mod.vf = urem i32 %Len, 4
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%n.vec = sub i32 %Len, %n.mod.vf
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
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%broadcast.splatinsert = insertelement <4 x i32> undef, i32 %index, i32 0
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%broadcast.splat = shufflevector <4 x i32> %broadcast.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
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%induction = add <4 x i32> %broadcast.splat, <i32 0, i32 1, i32 2, i32 3>
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%0 = add i32 %index, 0
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%1 = sext i32 %0 to i64
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%2 = getelementptr inbounds i32, i32* %Arr, i64 %1
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%3 = getelementptr inbounds i32, i32* %2, i32 0
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%4 = bitcast i32* %3 to <4 x i32>*
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%wide.load = load <4 x i32>, <4 x i32>* %4, align 4
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%5 = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %wide.load)
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%6 = sext i32 %0 to i64
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%7 = getelementptr inbounds i32, i32* %Arr, i64 %6
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%8 = getelementptr inbounds i32, i32* %7, i32 0
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%9 = bitcast i32* %8 to <4 x i32>*
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store <4 x i32> %5, <4 x i32>* %9, align 4
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%index.next = add i32 %index, 4
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%10 = icmp eq i32 %index.next, %n.vec
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br i1 %10, label %middle.block, label %vector.body
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middle.block: ; preds = %vector.body
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%cmp.n = icmp eq i32 %Len, %n.vec
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br i1 %cmp.n, label %for.cond.for.cond.cleanup_crit_edge, label %scalar.ph
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scalar.ph: ; preds = %middle.block, %for.body.lr.ph
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%bc.resume.val = phi i32 [ %n.vec, %middle.block ], [ 0, %for.body.lr.ph ]
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br label %for.body
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for.cond.for.cond.cleanup_crit_edge: ; preds = %middle.block, %for.inc
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.for.cond.cleanup_crit_edge, %entry
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br label %for.end
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for.body: ; preds = %for.inc, %scalar.ph
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%i.02 = phi i32 [ %bc.resume.val, %scalar.ph ], [ %inc, %for.inc ]
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%idxprom = sext i32 %i.02 to i64
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%arrayidx = getelementptr inbounds i32, i32* %Arr, i64 %idxprom
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%11 = load i32, i32* %arrayidx, align 4
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%12 = call i32 @llvm.bswap.i32(i32 %11)
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%idxprom1 = sext i32 %i.02 to i64
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%arrayidx2 = getelementptr inbounds i32, i32* %Arr, i64 %idxprom1
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store i32 %12, i32* %arrayidx2, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%inc = add nsw i32 %i.02, 1
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%cmp = icmp slt i32 %inc, %Len
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br i1 %cmp, label %for.body, label %for.cond.for.cond.cleanup_crit_edge
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for.end: ; preds = %for.cond.cleanup
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ret void
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}
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define dso_local <8 x i16> @test_halfword(<8 x i16> %a) local_unnamed_addr {
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; CHECK-LABEL: test_halfword:
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; CHECK: xxbrh vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%0 = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %a)
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ret <8 x i16> %0
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}
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define dso_local <2 x i64> @test_doubleword(<2 x i64> %a) local_unnamed_addr {
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; CHECK-LABEL: test_doubleword:
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; CHECK: xxbrd vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%0 = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
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ret <2 x i64> %0
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}
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define dso_local <1 x i128> @test_quadword(<1 x i128> %a) local_unnamed_addr {
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; CHECK-LABEL: test_quadword:
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; CHECK: xxbrq vs34, vs34
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; CHECK-NEXT: blr
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entry:
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%0 = call <1 x i128> @llvm.bswap.v1i128(<1 x i128> %a)
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ret <1 x i128> %0
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <1 x i128> @llvm.bswap.v1i128(<1 x i128>)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <2 x i64> @llvm.bswap.v2i64(<2 x i64>)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <8 x i16> @llvm.bswap.v8i16(<8 x i16>)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare i32 @llvm.bswap.i32(i32)
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; Function Attrs: nounwind readnone speculatable willreturn
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declare <4 x i32> @llvm.bswap.v4i32(<4 x i32>)
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97
test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
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97
test/Transforms/LoopVectorize/PowerPC/vectorize-bswap.ll
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@ -0,0 +1,97 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -loop-vectorize -mtriple=powerpc64le-unknown-unknown \
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; RUN: -force-target-max-vector-interleave=1 -mcpu=pwr9 < %s | FileCheck %s
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define dso_local void @test(i32* %Arr, i32 signext %Len) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 0, [[LEN:%.*]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[FOR_BODY_LR_PH:%.*]], label [[FOR_COND_CLEANUP:%.*]]
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; CHECK: for.body.lr.ph:
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[LEN]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i32 [[LEN]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i32 [[LEN]], [[N_MOD_VF]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> undef, i32 [[INDEX]], i32 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> undef, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[INDUCTION:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 1, i32 2, i32 3>
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[INDEX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[TMP0]] to i64
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, i32* [[ARR:%.*]], i64 [[TMP1]]
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; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, i32* [[TMP2]], i32 0
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; CHECK-NEXT: [[TMP4:%.*]] = bitcast i32* [[TMP3]] to <4 x i32>*
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, <4 x i32>* [[TMP4]], align 4
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; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> [[WIDE_LOAD]])
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; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP0]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, i32* [[ARR]], i64 [[TMP6]]
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; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 0
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; CHECK-NEXT: [[TMP9:%.*]] = bitcast i32* [[TMP8]] to <4 x i32>*
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; CHECK-NEXT: store <4 x i32> [[TMP5]], <4 x i32>* [[TMP9]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop !0
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[LEN]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_FOR_COND_CLEANUP_CRIT_EDGE:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[FOR_BODY_LR_PH]] ]
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.cond.for.cond.cleanup_crit_edge:
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; CHECK-NEXT: br label [[FOR_COND_CLEANUP]]
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; CHECK: for.cond.cleanup:
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; CHECK-NEXT: br label [[FOR_END:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[I_02:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INC:%.*]], [[FOR_INC:%.*]] ]
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; CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[I_02]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[ARR]], i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
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; CHECK-NEXT: [[TMP12:%.*]] = call i32 @llvm.bswap.i32(i32 [[TMP11]])
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; CHECK-NEXT: [[IDXPROM1:%.*]] = sext i32 [[I_02]] to i64
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; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, i32* [[ARR]], i64 [[IDXPROM1]]
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; CHECK-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX2]], align 4
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; CHECK-NEXT: br label [[FOR_INC]]
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; CHECK: for.inc:
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; CHECK-NEXT: [[INC]] = add nsw i32 [[I_02]], 1
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[INC]], [[LEN]]
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; CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_FOR_COND_CLEANUP_CRIT_EDGE]], !llvm.loop !2
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; CHECK: for.end:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp1 = icmp slt i32 0, %Len
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br i1 %cmp1, label %for.body.lr.ph, label %for.cond.cleanup
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for.body.lr.ph: ; preds = %entry
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br label %for.body
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for.cond.for.cond.cleanup_crit_edge: ; preds = %for.inc
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br label %for.cond.cleanup
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for.cond.cleanup: ; preds = %for.cond.for.cond.cleanup_crit_edge, %entry
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br label %for.end
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for.body: ; preds = %for.body.lr.ph, %for.inc
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%i.02 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.inc ]
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%idxprom = sext i32 %i.02 to i64
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%arrayidx = getelementptr inbounds i32, i32* %Arr, i64 %idxprom
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%0 = load i32, i32* %arrayidx, align 4
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%1 = call i32 @llvm.bswap.i32(i32 %0)
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%idxprom1 = sext i32 %i.02 to i64
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%arrayidx2 = getelementptr inbounds i32, i32* %Arr, i64 %idxprom1
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store i32 %1, i32* %arrayidx2, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%inc = add nsw i32 %i.02, 1
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%cmp = icmp slt i32 %inc, %Len
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br i1 %cmp, label %for.body, label %for.cond.for.cond.cleanup_crit_edge
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for.end: ; preds = %for.cond.cleanup
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ret void
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}
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; Function Attrs: nounwind readnone speculatable willreturn
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declare i32 @llvm.bswap.i32(i32)
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