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[AArch64] Extend AArch64RedundantCopyElimination to do simple copy propagation.
Summary:
Extend AArch64RedundantCopyElimination to catch cases where the register
that is known to be zero is COPY'd in the predecessor block. Before
this change, this pass would catch cases like:
CBZW %W0, <BB#1>
BB#1:
%W0 = COPY %WZR // removed
After this change, cases like the one below are also caught:
%W0 = COPY %W1
CBZW %W1, <BB#1>
BB#1:
%W0 = COPY %WZR // removed
This change results in a 4% increase in static copies removed by this
pass when compiling the llvm test-suite. It also fixes regressions
caused by doing post-RA copy propagation (a separate change to be put up
for review shortly).
Reviewers: junbuml, mcrosier, t.p.northover, qcolombet, MatzeB
Subscribers: aemerson, rengolin, llvm-commits
Differential Revision: https://reviews.llvm.org/D30113
llvm-svn: 295863
This commit is contained in:
Geoff Berry
parent
b65dbec9ff
commit
902f97ccb4
@ -43,6 +43,7 @@ namespace {
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class AArch64RedundantCopyElimination : public MachineFunctionPass {
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const MachineRegisterInfo *MRI;
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const TargetRegisterInfo *TRI;
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BitVector ClobberedRegs;
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public:
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static char ID;
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@ -76,6 +77,28 @@ static bool guaranteesZeroRegInBlock(MachineInstr &MI, MachineBasicBlock *MBB) {
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MBB != MI.getOperand(1).getMBB());
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}
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/// Remember what registers the specified instruction modifies.
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static void trackRegDefs(const MachineInstr &MI, BitVector &ClobberedRegs,
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const TargetRegisterInfo *TRI) {
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for (const MachineOperand &MO : MI.operands()) {
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if (MO.isRegMask()) {
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ClobberedRegs.setBitsNotInMask(MO.getRegMask());
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continue;
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}
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (!MO.isDef())
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continue;
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for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
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ClobberedRegs.set(*AI);
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}
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}
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bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
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// Check if the current basic block has a single predecessor.
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if (MBB->pred_size() != 1)
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@ -91,74 +114,134 @@ bool AArch64RedundantCopyElimination::optimizeCopy(MachineBasicBlock *MBB) {
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if (CompBr == PredMBB->end())
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return false;
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// Keep track of the earliest point in the PredMBB block where kill markers
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// need to be removed if a COPY is removed.
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MachineBasicBlock::iterator FirstUse;
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// Registers that are known to contain zeros at the start of MBB.
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SmallVector<MCPhysReg, 4> KnownZeroRegs;
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// Registers clobbered in PredMBB between CompBr instruction and current
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// instruction being checked in loop.
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ClobberedRegs.reset();
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++CompBr;
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do {
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--CompBr;
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if (guaranteesZeroRegInBlock(*CompBr, MBB))
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break;
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if (!guaranteesZeroRegInBlock(*CompBr, MBB))
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continue;
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KnownZeroRegs.push_back(CompBr->getOperand(0).getReg());
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FirstUse = CompBr;
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// Look backward in PredMBB for COPYs from the known zero reg to
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// find other registers that are known to be zero.
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for (auto PredI = CompBr;; --PredI) {
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if (PredI->isCopy()) {
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MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
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MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
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for (MCPhysReg KnownZeroReg : KnownZeroRegs) {
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if (ClobberedRegs[KnownZeroReg])
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continue;
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// If we have X = COPY Y, and Y is known to be zero, then now X is
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// known to be zero.
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if (CopySrcReg == KnownZeroReg && !ClobberedRegs[CopyDstReg]) {
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KnownZeroRegs.push_back(CopyDstReg);
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FirstUse = PredI;
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break;
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}
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// If we have X = COPY Y, and X is known to be zero, then now Y is
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// known to be zero.
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if (CopyDstReg == KnownZeroReg && !ClobberedRegs[CopySrcReg]) {
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KnownZeroRegs.push_back(CopySrcReg);
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FirstUse = PredI;
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break;
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}
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}
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}
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// Stop if we get to the beginning of PredMBB.
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if (PredI == PredMBB->begin())
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break;
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trackRegDefs(*PredI, ClobberedRegs, TRI);
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// Stop if all of the known-zero regs have been clobbered.
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if (all_of(KnownZeroRegs, [&](MCPhysReg KnownZeroReg) {
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return ClobberedRegs[KnownZeroReg];
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}))
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break;
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}
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break;
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} while (CompBr != PredMBB->begin() && CompBr->isTerminator());
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// We've not found a CBZ/CBNZ, time to bail out.
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if (!guaranteesZeroRegInBlock(*CompBr, MBB))
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// We've not found a known zero register, time to bail out.
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if (KnownZeroRegs.empty())
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return false;
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unsigned TargetReg = CompBr->getOperand(0).getReg();
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if (!TargetReg)
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return false;
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assert(TargetRegisterInfo::isPhysicalRegister(TargetReg) &&
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"Expect physical register");
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// Remember all registers aliasing with TargetReg.
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SmallSetVector<unsigned, 8> TargetRegs;
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for (MCRegAliasIterator AI(TargetReg, TRI, true); AI.isValid(); ++AI)
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TargetRegs.insert(*AI);
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bool Changed = false;
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// UsedKnownZeroRegs is the set of KnownZeroRegs that have had uses added to MBB.
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SmallSetVector<unsigned, 4> UsedKnownZeroRegs;
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MachineBasicBlock::iterator LastChange = MBB->begin();
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unsigned SmallestDef = TargetReg;
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// Remove redundant Copy instructions unless TargetReg is modified.
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// Remove redundant Copy instructions unless KnownZeroReg is modified.
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;) {
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MachineInstr *MI = &*I;
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++I;
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if (MI->isCopy() && MI->getOperand(0).isReg() &&
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MI->getOperand(1).isReg()) {
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unsigned DefReg = MI->getOperand(0).getReg();
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool RemovedCopy = false;
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if (MI->isCopy()) {
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MCPhysReg DefReg = MI->getOperand(0).getReg();
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MCPhysReg SrcReg = MI->getOperand(1).getReg();
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if ((SrcReg == AArch64::XZR || SrcReg == AArch64::WZR) &&
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!MRI->isReserved(DefReg) &&
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(TargetReg == DefReg || TRI->isSuperRegister(DefReg, TargetReg))) {
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DEBUG(dbgs() << "Remove redundant Copy : ");
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DEBUG((MI)->print(dbgs()));
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!MRI->isReserved(DefReg)) {
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for (MCPhysReg KnownZeroReg : KnownZeroRegs) {
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if (KnownZeroReg == DefReg ||
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TRI->isSuperRegister(DefReg, KnownZeroReg)) {
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DEBUG(dbgs() << "Remove redundant Copy : " << *MI);
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MI->eraseFromParent();
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Changed = true;
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LastChange = I;
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NumCopiesRemoved++;
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SmallestDef =
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TRI->isSubRegister(SmallestDef, DefReg) ? DefReg : SmallestDef;
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continue;
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MI->eraseFromParent();
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Changed = true;
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LastChange = I;
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NumCopiesRemoved++;
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UsedKnownZeroRegs.insert(KnownZeroReg);
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RemovedCopy = true;
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break;
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}
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}
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}
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}
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if (MI->modifiesRegister(TargetReg, TRI))
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// Skip to the next instruction if we removed the COPY from WZR/XZR.
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if (RemovedCopy)
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continue;
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// Remove any regs the MI clobbers from the KnownZeroRegs set.
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for (unsigned RI = 0; RI < KnownZeroRegs.size();)
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if (MI->modifiesRegister(KnownZeroRegs[RI], TRI)) {
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std::swap(KnownZeroRegs[RI], KnownZeroRegs[KnownZeroRegs.size() - 1]);
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KnownZeroRegs.pop_back();
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// Don't increment RI since we need to now check the swapped-in
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// KnownZeroRegs[RI].
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} else {
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++RI;
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}
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// Continue until the KnownZeroRegs set is empty.
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if (KnownZeroRegs.empty())
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break;
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}
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if (!Changed)
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return false;
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// Otherwise, we have to fixup the use-def chain, starting with the
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// CBZ/CBNZ. Conservatively mark as much as we can live.
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CompBr->clearRegisterKills(SmallestDef, TRI);
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// Add newly used regs to the block's live-in list if they aren't there
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// already.
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for (MCPhysReg KnownZeroReg : UsedKnownZeroRegs)
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if (!MBB->isLiveIn(KnownZeroReg))
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MBB->addLiveIn(KnownZeroReg);
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if (none_of(TargetRegs, [&](unsigned Reg) { return MBB->isLiveIn(Reg); }))
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MBB->addLiveIn(TargetReg);
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// Clear any kills of TargetReg between CompBr and the last removed COPY.
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// Clear kills in the range where changes were made. This is conservative,
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// but should be okay since kill markers are being phased out.
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for (MachineInstr &MMI : make_range(FirstUse, PredMBB->end()))
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MMI.clearKillInfo();
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for (MachineInstr &MMI : make_range(MBB->begin(), LastChange))
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MMI.clearRegisterKills(SmallestDef, TRI);
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MMI.clearKillInfo();
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return true;
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}
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@ -169,6 +252,7 @@ bool AArch64RedundantCopyElimination::runOnMachineFunction(
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return false;
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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ClobberedRegs.resize(TRI->getNumRegs());
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF)
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Changed |= optimizeCopy(&MBB);
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295
test/CodeGen/AArch64/machine-copy-remove.mir
Normal file
295
test/CodeGen/AArch64/machine-copy-remove.mir
Normal file
@ -0,0 +1,295 @@
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# RUN: llc -mtriple=aarch64--linux-gnu -run-pass=aarch64-copyelim %s -verify-machineinstrs -o - 2>&1 | FileCheck %s
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---
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# Check that bb.0 COPY is seen through to allow the bb.1 COPY of XZR to be removed.
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# CHECK-LABEL: name: test1
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# CHECK-NOT: COPY %xzr
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name: test1
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1
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%x0 = COPY %x1
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Similar to test1, but with reversed COPY.
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# CHECK-LABEL: name: test2
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# CHECK-NOT: COPY %xzr
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name: test2
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1
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%x1 = COPY %x0
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Similar to test1, but with a clobber that prevents removal of the XZR COPY.
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# CHECK-LABEL: name: test3
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# CHECK: COPY %xzr
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name: test3
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1, %x2
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%x0 = COPY %x1
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%x1 = LDRXui %x1, 0
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Similar to test2, but with a clobber that prevents removal of the XZR COPY.
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# CHECK-LABEL: name: test4
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# CHECK: COPY %xzr
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name: test4
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1, %x2
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%x1 = COPY %x0
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%x1 = LDRXui %x1, 0
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Similar to test2, but with a clobber that prevents removal of the XZR COPY.
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# CHECK-LABEL: name: test5
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# CHECK: COPY %xzr
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name: test5
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1, %x2
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%x1 = COPY %x0
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%x0 = LDRXui %x1, 0
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Similar to test1, but with two levels of COPYs.
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# CHECK-LABEL: name: test6
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# CHECK-NOT: COPY %xzr
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name: test6
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1, %x2
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%x2 = COPY %x0
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%x1 = COPY %x2
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Similar to test1, but with two levels of COPYs and a clobber preventing COPY of XZR removal.
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# CHECK-LABEL: name: test7
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# CHECK: COPY %xzr
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name: test7
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1, %x2
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%x2 = COPY %x0
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%x0 = LDRXui %x1, 0
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%x1 = COPY %x2
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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%x0 = COPY %xzr
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B %bb.3
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bb.2:
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successors: %bb.3
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liveins: %x1
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%x0 = LDRXui %x1, 0
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bb.3:
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liveins: %x0
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RET_ReallyLR implicit %x0
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...
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# Check that the TargetRegs vector clobber update loop in
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# AArch64RedundantCopyElimination::optimizeCopy works correctly.
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# CHECK-LABEL: name: test8
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# CHECK: x0 = COPY %xzr
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# CHECK: x1 = COPY %xzr
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name: test8
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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liveins: %x0, %x1
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%x1 = COPY %x0
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CBNZX %x1, %bb.2
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bb.1:
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successors: %bb.3
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liveins: %x0, %x2
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%x0, %x1 = LDPXi %x2, 0
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%x0 = COPY %xzr
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%x1 = COPY %xzr
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B %bb.3
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bb.2:
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||||
successors: %bb.3
|
||||
liveins: %x1
|
||||
|
||||
%x0 = LDRXui %x1, 0
|
||||
|
||||
bb.3:
|
||||
liveins: %x0
|
||||
|
||||
RET_ReallyLR implicit %x0
|
||||
|
||||
...
|
||||
# Check that copy isn't removed from a block with multiple predecessors.
|
||||
# CHECK-LABEL: name: test9
|
||||
# CHECK: x0 = COPY %xzr
|
||||
# CHECK-NEXT: B %bb.3
|
||||
name: test9
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.1, %bb.2
|
||||
liveins: %x0, %x1
|
||||
|
||||
CBNZX %x0, %bb.2
|
||||
|
||||
bb.1:
|
||||
successors: %bb.3
|
||||
liveins: %x0, %x2
|
||||
|
||||
%x0 = COPY %xzr
|
||||
B %bb.3
|
||||
|
||||
bb.2:
|
||||
successors: %bb.1, %bb.3
|
||||
liveins: %x1
|
||||
|
||||
%x0 = LDRXui %x1, 0
|
||||
|
||||
CBNZX %x1, %bb.1
|
||||
|
||||
bb.3:
|
||||
liveins: %x0
|
||||
|
||||
RET_ReallyLR implicit %x0
|
||||
|
||||
...
|
||||
Loading…
x
Reference in New Issue
Block a user