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[llvm-mca] Simplify code. NFC.
Now both method DispatchUnit::checkRAT() and DispatchUnit::canDispatch take as input an Instruction refrence instead of an instruction descriptor. This was requested by Simon in D44488 to simplify the diff. llvm-svn: 327640
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@ -36,7 +36,7 @@ void Backend::runCycle(unsigned Cycle) {
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std::unique_ptr<Instruction> NewIS(
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IB->createInstruction(STI, IR.first, *IR.second));
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const InstrDesc &Desc = NewIS->getDesc();
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if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(Desc))
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if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(*NewIS))
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break;
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Instruction *IS = NewIS.get();
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@ -199,7 +199,8 @@ void RetireControlUnit::dump() const {
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}
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#endif
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bool DispatchUnit::checkRAT(const InstrDesc &Desc) {
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bool DispatchUnit::checkRAT(const Instruction &Instr) {
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const InstrDesc &Desc = Instr.getDesc();
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unsigned NumWrites = Desc.Writes.size();
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if (RAT->isAvailable(NumWrites))
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return true;
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@ -233,7 +233,7 @@ class DispatchUnit {
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// stored into a vector `DispatchStall` which is always of size DS_LAST.
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std::vector<unsigned> DispatchStalls;
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bool checkRAT(const InstrDesc &Desc);
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bool checkRAT(const Instruction &Desc);
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bool checkRCU(const InstrDesc &Desc);
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bool checkScheduler(const InstrDesc &Desc);
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@ -260,9 +260,10 @@ public:
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bool isRCUEmpty() const { return RCU->isEmpty(); }
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bool canDispatch(const InstrDesc &Desc) {
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bool canDispatch(const Instruction &Inst) {
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const InstrDesc &Desc = Inst.getDesc();
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assert(isAvailable(Desc.NumMicroOps));
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return checkRCU(Desc) && checkRAT(Desc) && checkScheduler(Desc);
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return checkRCU(Desc) && checkRAT(Inst) && checkScheduler(Desc);
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}
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unsigned dispatch(unsigned IID, Instruction *NewInst,
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