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AMDGPU/GlobalISel: Handle G_ATOMICRMW_FADD
llvm-svn: 367509
This commit is contained in:
Matt Arsenault
parent
f6df754670
commit
90731e897e
@ -87,6 +87,7 @@ def : GINodeEquiv<G_ATOMICRMW_MIN, atomic_load_min_glue>;
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def : GINodeEquiv<G_ATOMICRMW_MAX, atomic_load_max_glue>;
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def : GINodeEquiv<G_ATOMICRMW_UMIN, atomic_load_umin_glue>;
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def : GINodeEquiv<G_ATOMICRMW_UMAX, atomic_load_umax_glue>;
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def : GINodeEquiv<G_ATOMICRMW_FADD, atomic_load_fadd_glue>;
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class GISelSop2Pat <
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@ -1395,6 +1395,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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case TargetOpcode::G_ATOMICRMW_MAX:
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case TargetOpcode::G_ATOMICRMW_UMIN:
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case TargetOpcode::G_ATOMICRMW_UMAX:
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case TargetOpcode::G_ATOMICRMW_FADD:
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return selectG_LOAD_ATOMICRMW(I, CoverageInfo);
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case TargetOpcode::G_SELECT:
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return selectG_SELECT(I);
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@ -593,6 +593,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
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}
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getActionDefinitionsBuilder(G_ATOMICRMW_FADD)
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.legalFor({{S32, LocalPtr}});
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// TODO: Pointer types, any 32-bit or 64-bit vector
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getActionDefinitionsBuilder(G_SELECT)
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.legalForCartesianProduct({S32, S64, S16, V2S32, V2S16, V4S16,
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@ -2229,6 +2229,7 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case AMDGPU::G_ATOMICRMW_MIN:
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case AMDGPU::G_ATOMICRMW_UMAX:
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case AMDGPU::G_ATOMICRMW_UMIN:
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case AMDGPU::G_ATOMICRMW_FADD:
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case AMDGPU::G_ATOMIC_CMPXCHG: {
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return getDefaultMappingAllVGPR(MI);
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}
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@ -0,0 +1,115 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
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# XUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# XUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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---
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name: atomicrmw_fadd_s32_local
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX6: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
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; GFX7-LABEL: name: atomicrmw_fadd_s32_local
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX7: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
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; GFX9-LABEL: name: atomicrmw_fadd_s32_local
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst 4, addrspace 3)
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$vgpr0 = COPY %2
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...
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---
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name: atomicrmw_fadd_s32_local_noret
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local_noret
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX7-LABEL: name: atomicrmw_fadd_s32_local_noret
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX9-LABEL: name: atomicrmw_fadd_s32_local_noret
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 0, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_ATOMICRMW_FADD %0(p3), %1 :: (load store seq_cst 4, addrspace 3)
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...
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---
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name: atomicrmw_fadd_s32_local_gep4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: atomicrmw_fadd_s32_local_gep4
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
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; GFX6: %3:vgpr_32, dead %5:sreg_64_xexec = V_ADD_I32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 %3, [[COPY1]], 0, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX6: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
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; GFX7-LABEL: name: atomicrmw_fadd_s32_local_gep4
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 4, 0, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX7: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
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; GFX9-LABEL: name: atomicrmw_fadd_s32_local_gep4
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_gfx9_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32_gfx9 [[COPY]], [[COPY1]], 4, 0, implicit $exec :: (load store seq_cst 4, addrspace 3)
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; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_gfx9_]]
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_CONSTANT i32 4
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%3:vgpr(p3) = G_GEP %0, %2
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%4:vgpr(s32) = G_ATOMICRMW_FADD %3(p3), %1 :: (load store seq_cst 4, addrspace 3)
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$vgpr0 = COPY %4
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...
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17
test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd.mir
Normal file
17
test/CodeGen/AMDGPU/GlobalISel/legalize-atomicrmw-fadd.mir
Normal file
@ -0,0 +1,17 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: atomicrmw_fadd_local_i32
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: atomicrmw_fadd_local_i32
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; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
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; CHECK: [[ATOMICRMW_FADD:%[0-9]+]]:_(s32) = G_ATOMICRMW_FADD [[COPY]](p3), [[COPY1]] :: (load store seq_cst 4, addrspace 3)
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%0:_(p3) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = G_ATOMICRMW_FADD %0, %1 :: (load store seq_cst 4, addrspace 3)
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...
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@ -0,0 +1,21 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
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---
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name: atomicrmw_fadd_local_i32_ss
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legalized: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; CHECK-LABEL: name: atomicrmw_fadd_local_i32_ss
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; CHECK: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0
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; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)
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; CHECK: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)
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; CHECK: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY2]](p3), [[COPY3]] :: (load store seq_cst 4, addrspace 3)
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%0:_(p3) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = G_ATOMICRMW_FADD %0, %1 :: (load store seq_cst 4, addrspace 3)
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...
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