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This commit introduces two fake instructions MORESTACK_RET and
MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET followed by a MOV respectively. Having a fake instruction prevents the verifier from seeing a MachineBasicBlock end with a non-terminator (MOV). It also prevents the rather eccentric case of a MachineBasicBlock ending with RET but having successors nevertheless. Patch by Sanjoy Das. llvm-svn: 143062
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@ -1336,26 +1336,16 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
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// The MOV R10, RAX needs to be in a different block, since the RET we emit in
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// The MOV R10, RAX needs to be in a different block, since the RET we emit in
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// allocMBB needs to be last (terminating) instruction.
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// allocMBB needs to be last (terminating) instruction.
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MachineBasicBlock *restoreR10MBB = NULL;
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if (IsNested)
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restoreR10MBB = MF.CreateMachineBasicBlock();
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for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
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for (MachineBasicBlock::livein_iterator i = prologueMBB.livein_begin(),
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e = prologueMBB.livein_end(); i != e; i++) {
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e = prologueMBB.livein_end(); i != e; i++) {
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allocMBB->addLiveIn(*i);
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allocMBB->addLiveIn(*i);
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checkMBB->addLiveIn(*i);
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checkMBB->addLiveIn(*i);
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if (IsNested)
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restoreR10MBB->addLiveIn(*i);
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}
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}
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if (IsNested) {
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if (IsNested)
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allocMBB->addLiveIn(X86::R10);
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allocMBB->addLiveIn(X86::R10);
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restoreR10MBB->addLiveIn(X86::RAX);
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}
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if (IsNested)
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MF.push_front(restoreR10MBB);
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MF.push_front(allocMBB);
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MF.push_front(allocMBB);
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MF.push_front(checkMBB);
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MF.push_front(checkMBB);
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@ -1425,18 +1415,12 @@ X86FrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
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if (!Is64Bit)
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if (!Is64Bit)
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BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP)
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BuildMI(allocMBB, DL, TII.get(X86::ADD32ri), X86::ESP).addReg(X86::ESP)
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.addImm(8);
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.addImm(8);
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BuildMI(allocMBB, DL, TII.get(X86::RET));
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if (IsNested)
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if (IsNested)
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BuildMI(restoreR10MBB, DL, TII.get(X86::MOV64rr), X86::R10)
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BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET_RESTORE_R10));
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.addReg(X86::RAX);
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else
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BuildMI(allocMBB, DL, TII.get(X86::MORESTACK_RET));
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if (IsNested) {
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allocMBB->addSuccessor(restoreR10MBB);
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restoreR10MBB->addSuccessor(&prologueMBB);
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} else {
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allocMBB->addSuccessor(&prologueMBB);
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allocMBB->addSuccessor(&prologueMBB);
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}
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checkMBB->addSuccessor(allocMBB);
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checkMBB->addSuccessor(allocMBB);
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checkMBB->addSuccessor(&prologueMBB);
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checkMBB->addSuccessor(&prologueMBB);
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@ -149,6 +149,24 @@ def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
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}
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}
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//===----------------------------------------------------------------------===//
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// Pseudo instructions used by segmented stacks.
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//
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// This is lowered into a RET instruction by MCInstLower. We need
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// this so that we don't have to have a MachineBasicBlock which ends
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// with a RET and also has successors.
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let isPseudo = 1 in {
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def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
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"", []>;
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// This instruction is lowered to a RET followed by a MOV. The two
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// instructions are not generated on a higher level since then the
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// verifier sees a MachineBasicBlock ending with a non-terminator.
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def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
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"", []>;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Alias Instructions
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// Alias Instructions
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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@ -527,6 +527,22 @@ ReSimplify:
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case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
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case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
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case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
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case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
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case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
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case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
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case X86::MORESTACK_RET:
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OutMI.setOpcode(X86::RET);
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break;
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case X86::MORESTACK_RET_RESTORE_R10: {
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MCInst retInst;
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OutMI.setOpcode(X86::MOV64rr);
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OutMI.addOperand(MCOperand::CreateReg(X86::R10));
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OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
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retInst.setOpcode(X86::RET);
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AsmPrinter.OutStreamer.EmitInstruction(retInst);
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break;
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}
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}
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}
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}
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}
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@ -82,6 +82,6 @@ define i32 @test_nested(i32 * nest %closure, i32 %other) {
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; X64-NEXT: movabsq $0, %r11
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; X64-NEXT: movabsq $0, %r11
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; X64-NEXT: callq __morestack
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; X64-NEXT: callq __morestack
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; X64-NEXT: ret
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; X64-NEXT: ret
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; X64: movq %rax, %r10
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; X64-NEXT: movq %rax, %r10
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}
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}
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