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[Hexagon] Mark dead defs as <dead> in expand-condsets
The code in updateDeadFlags removed unnecessary <dead> flags, but there can be cases where such a flag is not set, and yet a register has become dead. For example, if a mux with identical inputs is replaced with a COPY, the predicate register may no longer be used after that. llvm-svn: 297032
This commit is contained in:
Krzysztof Parzyszek
parent
fbbcfd906f
commit
90d780b0a6
@ -362,14 +362,16 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
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if (Range.empty())
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return;
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auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool {
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// Return two booleans: { def-modifes-reg, def-covers-reg }.
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auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
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if (!Op.isReg() || !Op.isDef())
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return false;
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return { false, false };
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unsigned DR = Op.getReg(), DSR = Op.getSubReg();
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if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
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return false;
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return { false, false };
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LaneBitmask SLM = getLaneMask(DR, DSR);
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return (SLM & LM).any();
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LaneBitmask A = SLM & LM;
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return { A.any(), A == SLM };
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};
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// The splitting step will create pairs of predicated definitions without
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@ -453,20 +455,27 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
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// Remove <dead> flags from all defs that are not dead after live range
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// extension, and collect all def operands. They will be used to generate
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// the necessary implicit uses.
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// At the same time, add <dead> flag to all defs that are actually dead.
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// This can happen, for example, when a mux with identical inputs is
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// replaced with a COPY: the use of the predicate register disappears and
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// the dead can become dead.
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std::set<RegisterRef> DefRegs;
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for (auto &Seg : Range) {
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if (!Seg.start.isRegister())
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continue;
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MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
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for (auto &Op : DefI->operands()) {
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if (Seg.start.isDead() || !IsRegDef(Op))
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continue;
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DefRegs.insert(Op);
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Op.setIsDead(false);
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auto P = IsRegDef(Op);
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if (P.second && Seg.end.isDead()) {
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Op.setIsDead(true);
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} else if (P.first) {
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DefRegs.insert(Op);
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Op.setIsDead(false);
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}
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}
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}
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// Finally, add implicit uses to each predicated def that is reached
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// Now, add implicit uses to each predicated def that is reached
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// by other defs.
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for (auto &Seg : Range) {
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if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot()))
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@ -486,6 +495,7 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
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for (RegisterRef R : ImpUses)
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MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
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}
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}
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void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
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@ -622,6 +632,12 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
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bool ReadUndef = MD.isUndef();
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MachineBasicBlock::iterator At = MI;
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auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void {
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for (auto &Op : MI.operands())
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if (Op.isReg())
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UpdRegs.insert(Op.getReg());
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};
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// If this is a mux of the same register, just replace it with COPY.
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// Ideally, this would happen earlier, so that register coalescing would
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// see it.
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@ -630,6 +646,8 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
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if (ST.isReg() && SF.isReg()) {
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RegisterRef RT(ST);
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if (RT == RegisterRef(SF)) {
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// Copy regs to update first.
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updateRegs(MI);
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MI.setDesc(HII->get(TargetOpcode::COPY));
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unsigned S = getRegState(ST);
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while (MI.getNumOperands() > 1)
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@ -651,9 +669,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
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LIS->InsertMachineInstrInMaps(*TfrF);
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// Will need to recalculate live intervals for all registers in MI.
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for (auto &Op : MI.operands())
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if (Op.isReg())
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UpdRegs.insert(Op.getReg());
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updateRegs(MI);
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removeInstr(MI);
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return true;
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54
test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
Normal file
54
test/CodeGen/Hexagon/expand-condsets-dead-bad.ll
Normal file
@ -0,0 +1,54 @@
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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; REQUIRES: asserts
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; Check for some output other than crashing.
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; CHECK: bitsset
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @fred() local_unnamed_addr #0 {
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b0:
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%v1 = load i32, i32* undef, align 4
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%v2 = and i32 %v1, 603979776
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%v3 = trunc i32 %v2 to i30
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switch i30 %v3, label %b23 [
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i30 -536870912, label %b4
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i30 -469762048, label %b5
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]
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b4: ; preds = %b0
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unreachable
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b5: ; preds = %b0
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%v6 = load i32, i32* undef, align 4
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br i1 undef, label %b7, label %b8
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b7: ; preds = %b5
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br label %b9
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b8: ; preds = %b5
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br label %b9
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b9: ; preds = %b8, %b7
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%v10 = load i32, i32* undef, align 4
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%v11 = load i32, i32* undef, align 4
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%v12 = mul nsw i32 %v11, %v10
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%v13 = ashr i32 %v12, 13
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%v14 = mul nsw i32 %v13, %v13
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%v15 = zext i32 %v14 to i64
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%v16 = mul nsw i32 %v6, %v6
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%v17 = zext i32 %v16 to i64
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%v18 = lshr i64 %v17, 5
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%v19 = select i1 undef, i64 %v18, i64 %v17
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%v20 = mul nuw nsw i64 %v19, %v15
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%v21 = trunc i64 %v20 to i32
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%v22 = and i32 %v21, 2147483647
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store i32 %v22, i32* undef, align 4
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unreachable
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b23: ; preds = %b0
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" }
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45
test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
Normal file
45
test/CodeGen/Hexagon/expand-condsets-dead-pred.ll
Normal file
@ -0,0 +1,45 @@
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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; REQUIRES: asserts
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; Check for some output (as opposed to a crash).
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; CHECK: loop0
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target triple = "hexagon"
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@x = external local_unnamed_addr global [80 x i32], align 8
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; Function Attrs: nounwind
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define void @fred() local_unnamed_addr #0 {
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b0:
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br label %b1
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b1: ; preds = %b20, %b0
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br label %b2
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b2: ; preds = %b2, %b1
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%v3 = phi i32 [ 0, %b1 ], [ %v17, %b2 ]
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%v4 = phi i32 [ 0, %b1 ], [ %v16, %b2 ]
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%v5 = phi i32 [ undef, %b1 ], [ %v18, %b2 ]
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%v6 = load i32, i32* undef, align 8
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%v7 = icmp sgt i32 %v6, undef
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%v8 = select i1 %v7, i32 %v3, i32 %v4
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%v9 = select i1 undef, i32 0, i32 %v8
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%v10 = select i1 undef, i32 undef, i32 %v9
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%v11 = select i1 undef, i32 0, i32 %v10
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%v12 = icmp sgt i32 undef, 0
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%v13 = select i1 %v12, i32 undef, i32 %v11
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%v14 = select i1 false, i32 undef, i32 %v13
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%v15 = select i1 false, i32 undef, i32 %v14
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%v16 = select i1 false, i32 undef, i32 %v15
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%v17 = add nsw i32 %v3, 8
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%v18 = add i32 %v5, -8
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%v19 = icmp eq i32 %v18, 0
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br i1 %v19, label %b20, label %b2
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b20: ; preds = %b2
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%v21 = getelementptr inbounds [80 x i32], [80 x i32]* @x, i32 0, i32 %v16
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store i32 -2000, i32* %v21, align 4
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br label %b1
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
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