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[ARM] Assign cost of scaling for Cortex-R52

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This patch assigns cost of the scaling used in addressing for Cortex-R52.

On Cortex-R52 a negated register offset takes longer than a non-negated
register offset, in a register-offset addressing mode.

Differential Revision: http://reviews.llvm.org/D25670

Reviewer: jmolloy
llvm-svn: 284460
This commit is contained in:
Javed Absar 2016-10-18 09:08:54 +00:00
parent 293c1a3deb
commit 90db73a094
2 changed files with 6 additions and 5 deletions
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3
lib/Target/ARM/ARM.td
View File

@ -823,7 +823,8 @@ def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
FeatureCrypto,
FeatureCRC]>;
def : ProcNoItin<"cortex-r52", [ARMv8r, ProcR52]>;
def : ProcNoItin<"cortex-r52", [ARMv8r, ProcR52,
FeatureFPAO]>;
//===----------------------------------------------------------------------===//
// Register File Description

8
test/CodeGen/ARM/lsr-scale-addr-mode.ll
View File

@ -1,8 +1,9 @@
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
; Should use scaled addressing mode.
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A53
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A57
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF
; Should not generate negated register offset
define void @sintzero(i32* %a) nounwind {
@ -23,6 +24,5 @@ return: ; preds = %cond_next
}
; CHECK: lsl{{.*}}#2]
; CHECK-NONEGOFF-A53: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
; CHECK-NONEGOFF-A57: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
; CHECK-NONEGOFF: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]