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https://github.com/RPCS3/llvm-mirror.git
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AMDGPU/GlobalISel: Select simple local stores
llvm-svn: 367504
This commit is contained in:
Matt Arsenault
parent
c6739e6709
commit
9156809a6f
@ -74,6 +74,7 @@ def gi_ds_1addr_1offset :
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// directly before before selecting a glue-less load, so hide this
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// distinction.
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def : GINodeEquiv<G_LOAD, AMDGPUld_glue>;
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def : GINodeEquiv<G_STORE, AMDGPUst_glue>;
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@ -840,17 +840,22 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
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return Ret;
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}
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bool AMDGPUInstructionSelector::selectG_STORE(MachineInstr &I) const {
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bool AMDGPUInstructionSelector::selectG_STORE(
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MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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DebugLoc DL = I.getDebugLoc();
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unsigned PtrSize = RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI);
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if (PtrSize != 64) {
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LLVM_DEBUG(dbgs() << "Unhandled address space\n");
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return false;
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const DebugLoc &DL = I.getDebugLoc();
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LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
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if (PtrTy.getSizeInBits() != 64) {
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initM0(I);
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return selectImpl(I, CoverageInfo);
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}
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if (selectImpl(I, CoverageInfo))
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return true;
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unsigned StoreSize = RBI.getSizeInBits(I.getOperand(0).getReg(), MRI, TRI);
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unsigned Opcode;
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@ -1243,8 +1248,7 @@ bool AMDGPUInstructionSelector::hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const {
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return false;
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}
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bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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void AMDGPUInstructionSelector::initM0(MachineInstr &I) const {
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MachineBasicBlock *BB = I.getParent();
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MachineFunction *MF = BB->getParent();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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@ -1257,7 +1261,11 @@ bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I,
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BuildMI(*BB, &I, I.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), AMDGPU::M0)
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.addImm(-1);
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}
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}
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bool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I,
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CodeGenCoverage &CoverageInfo) const {
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initM0(I);
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return selectImpl(I, CoverageInfo);
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}
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@ -1377,12 +1385,11 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I,
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return selectImpl(I, CoverageInfo);
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case TargetOpcode::G_LOAD:
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return selectG_LOAD(I, CoverageInfo);
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case TargetOpcode::G_SELECT:
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return selectG_SELECT(I);
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case TargetOpcode::G_STORE:
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if (selectImpl(I, CoverageInfo))
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return true;
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return selectG_STORE(I);
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return selectG_STORE(I, CoverageInfo);
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case TargetOpcode::G_TRUNC:
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return selectG_TRUNC(I);
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case TargetOpcode::G_SEXT:
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@ -90,9 +90,11 @@ private:
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void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
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SmallVectorImpl<GEPInfo> &AddrInfo) const;
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bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
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void initM0(MachineInstr &I) const;
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bool selectG_LOAD(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool selectG_STORE(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
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bool selectG_SELECT(MachineInstr &I) const;
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bool selectG_STORE(MachineInstr &I) const;
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bool selectG_BRCOND(MachineInstr &I) const;
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bool selectG_FRAME_INDEX(MachineInstr &I) const;
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@ -493,11 +493,13 @@ def load_align16_local : PatFrag <(ops node:$ptr), (load_local node:$ptr)> {
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def store_align8_local: PatFrag<(ops node:$val, node:$ptr),
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(store_local node:$val, node:$ptr)>, Aligned<8> {
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let IsStore = 1;
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let IsTruncStore = 0;
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}
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def store_align16_local: PatFrag<(ops node:$val, node:$ptr),
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(store_local node:$val, node:$ptr)>, Aligned<16> {
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let IsStore = 1;
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let IsTruncStore = 0;
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}
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@ -668,7 +668,7 @@ def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
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class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
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(frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
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(inst $ptr, $value, offset:$offset, (i1 gds))
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(inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
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>;
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multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
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@ -475,13 +475,34 @@ def store_glue_align8 : PatFrag<(ops node:$val, node:$ptr),
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def store_glue_align16 : PatFrag<(ops node:$val, node:$ptr),
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(store_glue node:$val, node:$ptr)>, Aligned<16>;
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def store_local_m0 : StoreFrag<store_glue>, LocalAddress;
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def truncstorei8_local_m0 : StoreFrag<truncstorei8_glue>, LocalAddress;
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def truncstorei16_local_m0 : StoreFrag<truncstorei16_glue>, LocalAddress;
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def atomic_store_local_m0 : StoreFrag<AMDGPUatomic_st_glue>, LocalAddress;
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def store_local_m0 : PatFrag<(ops node:$val, node:$ptr),
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(unindexedstore_glue node:$val, node:$ptr)> {
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let IsStore = 1;
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let IsTruncStore = 0;
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}
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def store_align8_local_m0 : StoreFrag<store_glue_align8>, LocalAddress;
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def store_align16_local_m0 : StoreFrag<store_glue_align16>, LocalAddress;
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def truncstorei8_local_m0 : PatFrag<(ops node:$val, node:$ptr),
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(unindexedstore_glue node:$val, node:$ptr)> {
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let IsStore = 1;
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let MemoryVT = i8;
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}
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def truncstorei16_local_m0 : PatFrag<(ops node:$val, node:$ptr),
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(unindexedstore_glue node:$val, node:$ptr)> {
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let IsStore = 1;
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let MemoryVT = i16;
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}
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// FIXME: atomic store doesn't work.
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def atomic_store_local_m0 : StoreFrag<AMDGPUatomic_st_glue>, LocalAddress;
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def store_align8_local_m0 : StoreFrag<store_glue_align8>, LocalAddress {
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let IsTruncStore = 0;
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}
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def store_align16_local_m0 : StoreFrag<store_glue_align16>, LocalAddress {
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let IsTruncStore = 0;
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}
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}
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def si_setcc_uniform : PatFrag <
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262
test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
Normal file
262
test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
Normal file
@ -0,0 +1,262 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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---
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name: store_local_s32_to_4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_local_s32_to_4
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
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; GFX7-LABEL: name: store_local_s32_to_4
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: DS_WRITE_B32 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store 4, addrspace 3)
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; GFX9-LABEL: name: store_local_s32_to_4
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: DS_WRITE_B32_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store 4, addrspace 3)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(p3) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 3)
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...
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---
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name: store_local_s32_to_2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_local_s32_to_2
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: DS_WRITE_B16 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store 2, addrspace 3)
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; GFX7-LABEL: name: store_local_s32_to_2
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: DS_WRITE_B16 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store 2, addrspace 3)
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; GFX9-LABEL: name: store_local_s32_to_2
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: DS_WRITE_B16_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store 2, addrspace 3)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(p3) = COPY $vgpr1
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G_STORE %0, %1 :: (store 2, align 2, addrspace 3)
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...
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---
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name: store_local_s32_to_1
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_local_s32_to_1
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: DS_WRITE_B8 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store 1, addrspace 3)
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; GFX7-LABEL: name: store_local_s32_to_1
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: DS_WRITE_B8 [[COPY1]], [[COPY]], 0, 0, implicit $m0, implicit $exec :: (store 1, addrspace 3)
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; GFX9-LABEL: name: store_local_s32_to_1
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: DS_WRITE_B8_gfx9 [[COPY1]], [[COPY]], 0, 0, implicit $exec :: (store 1, addrspace 3)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(p3) = COPY $vgpr1
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G_STORE %0, %1 :: (store 1, align 1, addrspace 3)
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...
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---
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name: store_local_v2s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_local_v2s16
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: G_STORE [[COPY]](<2 x s16>), [[COPY1]](p3) :: (store 4, addrspace 3)
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; GFX7-LABEL: name: store_local_v2s16
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: G_STORE [[COPY]](<2 x s16>), [[COPY1]](p3) :: (store 4, addrspace 3)
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; GFX9-LABEL: name: store_local_v2s16
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
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; GFX9: G_STORE [[COPY]](<2 x s16>), [[COPY1]](p3) :: (store 4, addrspace 3)
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(p3) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 3)
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...
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---
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name: store_local_p3
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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scratchWaveOffsetReg: $sgpr4
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: store_local_p3
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: G_STORE [[COPY]](p3), [[COPY1]](p3) :: (store 4, addrspace 3)
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; GFX7-LABEL: name: store_local_p3
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; GFX7: liveins: $vgpr0, $vgpr1
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; GFX7: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: G_STORE [[COPY]](p3), [[COPY1]](p3) :: (store 4, addrspace 3)
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; GFX9-LABEL: name: store_local_p3
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr(p3) = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY $vgpr1
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; GFX9: G_STORE [[COPY]](p3), [[COPY1]](p3) :: (store 4, addrspace 3)
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%0:vgpr(p3) = COPY $vgpr0
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%1:vgpr(p3) = COPY $vgpr1
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G_STORE %0, %1 :: (store 4, align 4, addrspace 3)
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...
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---
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|
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name: store_local_s32_to_1_constant_4095
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
; GFX6-LABEL: name: store_local_s32_to_1_constant_4095
|
||||
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
|
||||
; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GFX6: $m0 = S_MOV_B32 -1
|
||||
; GFX6: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 1, addrspace 3)
|
||||
; GFX7-LABEL: name: store_local_s32_to_1_constant_4095
|
||||
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
|
||||
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GFX7: $m0 = S_MOV_B32 -1
|
||||
; GFX7: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 1, addrspace 3)
|
||||
; GFX9-LABEL: name: store_local_s32_to_1_constant_4095
|
||||
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4095, implicit $exec
|
||||
; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GFX9: DS_WRITE_B8_gfx9 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (store 1, addrspace 3)
|
||||
%0:vgpr(p3) = G_CONSTANT i32 4095
|
||||
%1:vgpr(s32) = G_CONSTANT i32 0
|
||||
G_STORE %1, %0 :: (store 1, align 1, addrspace 3)
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: store_local_s32_to_1_constant_4096
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
machineFunctionInfo:
|
||||
scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
|
||||
scratchWaveOffsetReg: $sgpr4
|
||||
stackPtrOffsetReg: $sgpr32
|
||||
stack:
|
||||
- { id: 0, size: 4096, alignment: 4 }
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
|
||||
; GFX6-LABEL: name: store_local_s32_to_1_constant_4096
|
||||
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
|
||||
; GFX6: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GFX6: $m0 = S_MOV_B32 -1
|
||||
; GFX6: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 1, addrspace 3)
|
||||
; GFX7-LABEL: name: store_local_s32_to_1_constant_4096
|
||||
; GFX7: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
|
||||
; GFX7: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GFX7: $m0 = S_MOV_B32 -1
|
||||
; GFX7: DS_WRITE_B8 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $m0, implicit $exec :: (store 1, addrspace 3)
|
||||
; GFX9-LABEL: name: store_local_s32_to_1_constant_4096
|
||||
; GFX9: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4096, implicit $exec
|
||||
; GFX9: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
|
||||
; GFX9: DS_WRITE_B8_gfx9 [[V_MOV_B32_e32_]], [[V_MOV_B32_e32_1]], 0, 0, implicit $exec :: (store 1, addrspace 3)
|
||||
%0:vgpr(p3) = G_CONSTANT i32 4096
|
||||
%1:vgpr(s32) = G_CONSTANT i32 0
|
||||
G_STORE %1, %0 :: (store 1, align 1, addrspace 3)
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user