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[RISCV] Introduce codegen patterns for RV64M-only instructions
As discussed on llvm-dev <http://lists.llvm.org/pipermail/llvm-dev/2018-December/128497.html>, we have to be careful when trying to select the *w RV64M instructions. i32 is not a legal type for RV64 in the RISC-V backend, so operations have been promoted by the time they reach instruction selection. Information about whether the operation was originally a 32-bit operations has been lost, and it's easy to write incorrect patterns. Similarly to the variable 32-bit shifts, a DAG combine on ANY_EXTEND will produce a SIGN_EXTEND if this is likely to result in sdiv/udiv/urem being selected (and so save instructions to sext/zext the input operands). Differential Revision: https://reviews.llvm.org/D53230 llvm-svn: 350993
This commit is contained in:
Alex Bradbury
parent
4a042ffefe
commit
9164425b9b
@ -525,6 +525,20 @@ static bool isVariableShift(SDValue Val) {
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}
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}
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// Returns true if the given node is an sdiv, udiv, or urem with non-constant
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// operands.
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static bool isVariableSDivUDivURem(SDValue Val) {
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switch (Val.getOpcode()) {
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default:
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return false;
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case ISD::SDIV:
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case ISD::UDIV:
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case ISD::UREM:
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return Val.getOperand(0).getOpcode() != ISD::Constant &&
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Val.getOperand(1).getOpcode() != ISD::Constant;
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}
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}
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SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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@ -552,12 +566,14 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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N, DAG.getNode(N->getOpcode(), DL, LHS.getValueType(), LHS, NewRHS));
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}
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case ISD::ANY_EXTEND: {
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// If any-extending an i32 variable-length shift to i64, then instead
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// sign-extend in order to increase the chance of being able to select the
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// sllw/srlw/sraw instruction.
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// If any-extending an i32 variable-length shift or sdiv/udiv/urem to i64,
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// then instead sign-extend in order to increase the chance of being able
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// to select the sllw/srlw/sraw/divw/divuw/remuw instructions.
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SDValue Src = N->getOperand(0);
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if (N->getValueType(0) != MVT::i64 || Src.getValueType() != MVT::i32 ||
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!isVariableShift(Src))
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if (N->getValueType(0) != MVT::i64 || Src.getValueType() != MVT::i32)
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break;
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if (!isVariableShift(Src) &&
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!(Subtarget.hasStdExtM() && isVariableSDivUDivURem(Src)))
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break;
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SDLoc DL(N);
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return DCI.CombineTo(N, DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Src));
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@ -49,3 +49,34 @@ def : PatGprGpr<udiv, DIVU>;
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def : PatGprGpr<srem, REM>;
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def : PatGprGpr<urem, REMU>;
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} // Predicates = [HasStdExtM]
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let Predicates = [HasStdExtM, IsRV64] in {
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def : Pat<(sext_inreg (mul GPR:$rs1, GPR:$rs2), i32),
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(MULW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (sdiv (sexti32 GPR:$rs1),
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(sexti32 GPR:$rs2)), i32),
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(DIVW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(zexti32 (sdiv (sexti32 GPR:$rs1),
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(sexti32 GPR:$rs2))),
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(SRLI (SLLI (DIVW GPR:$rs1, GPR:$rs2), 32), 32)>;
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def : Pat<(sext_inreg (udiv (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)), i32),
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(DIVUW GPR:$rs1, GPR:$rs2)>;
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// It's cheaper to perform a divuw and zero-extend the result than to
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// zero-extend both inputs to a udiv.
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def : Pat<(udiv (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff)),
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(SRLI (SLLI (DIVUW GPR:$rs1, GPR:$rs2), 32), 32)>;
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// Although the sexti32 operands may not have originated from an i32 srem,
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// this pattern is safe as it is impossible for two sign extended inputs to
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// produce a result where res[63:32]=0 and res[31]=1.
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def : Pat<(srem (sexti32 GPR:$rs1), (sexti32 GPR:$rs2)),
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(REMW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (srem (sexti32 GPR:$rs1),
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(sexti32 GPR:$rs2)), i32),
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(REMW GPR:$rs1, GPR:$rs2)>;
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def : Pat<(sext_inreg (urem (zexti32 GPR:$rs1), (zexti32 GPR:$rs2)), i32),
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(REMUW GPR:$rs1, GPR:$rs2)>;
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// It's cheaper to perform a remuw and zero-extend the result than to
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// zero-extend both inputs to a urem.
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def : Pat<(urem (and GPR:$rs1, 0xffffffff), (and GPR:$rs2, 0xffffffff)),
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(SRLI (SLLI (REMUW GPR:$rs1, GPR:$rs2), 32), 32)>;
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} // Predicates = [HasStdExtM, IsRV64]
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@ -3,6 +3,10 @@
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IM %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IM %s
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define i32 @udiv(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: udiv:
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@ -18,6 +22,24 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: divu a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: udiv:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: srli a1, a1, 32
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; RV64I-NEXT: call __udivdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: udiv:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: divuw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = udiv i32 %a, %b
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ret i32 %1
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}
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@ -40,6 +62,34 @@ define i32 @udiv_constant(i32 %a) nounwind {
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; RV32IM-NEXT: mulhu a0, a0, a1
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; RV32IM-NEXT: srli a0, a0, 2
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: udiv_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: addi a1, zero, 5
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; RV64I-NEXT: call __udivdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: udiv_constant:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: slli a0, a0, 32
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; RV64IM-NEXT: srli a0, a0, 32
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; RV64IM-NEXT: lui a1, 1035469
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; RV64IM-NEXT: addiw a1, a1, -819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -819
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; RV64IM-NEXT: mulhu a0, a0, a1
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; RV64IM-NEXT: srli a0, a0, 2
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; RV64IM-NEXT: ret
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%1 = udiv i32 %a, 5
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ret i32 %1
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}
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@ -54,6 +104,16 @@ define i32 @udiv_pow2(i32 %a) nounwind {
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: srli a0, a0, 3
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: udiv_pow2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: srliw a0, a0, 3
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: udiv_pow2:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: srliw a0, a0, 3
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; RV64IM-NEXT: ret
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%1 = udiv i32 %a, 8
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ret i32 %1
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}
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@ -76,6 +136,20 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind {
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: udiv64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __udivdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: udiv64:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: divu a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = udiv i64 %a, %b
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ret i64 %1
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}
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@ -102,6 +176,30 @@ define i64 @udiv64_constant(i64 %a) nounwind {
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: udiv64_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: addi a1, zero, 5
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; RV64I-NEXT: call __udivdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: udiv64_constant:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: lui a1, 1035469
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; RV64IM-NEXT: addiw a1, a1, -819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, -819
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; RV64IM-NEXT: mulhu a0, a0, a1
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; RV64IM-NEXT: srli a0, a0, 2
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; RV64IM-NEXT: ret
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%1 = udiv i64 %a, 5
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ret i64 %1
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}
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@ -120,6 +218,22 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind {
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: div a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: sdiv:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: sext.w a1, a1
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; RV64I-NEXT: call __divdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: sdiv:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: divw a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = sdiv i32 %a, %b
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ret i32 %1
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}
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@ -144,6 +258,34 @@ define i32 @sdiv_constant(i32 %a) nounwind {
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; RV32IM-NEXT: srai a0, a0, 1
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: sdiv_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sext.w a0, a0
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; RV64I-NEXT: addi a1, zero, 5
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; RV64I-NEXT: call __divdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: sdiv_constant:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a0, a0
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; RV64IM-NEXT: lui a1, 13107
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; RV64IM-NEXT: addiw a1, a1, 819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, 819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, 819
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; RV64IM-NEXT: slli a1, a1, 13
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; RV64IM-NEXT: addi a1, a1, 1639
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; RV64IM-NEXT: mulh a0, a0, a1
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; RV64IM-NEXT: srli a1, a0, 63
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; RV64IM-NEXT: srai a0, a0, 1
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; RV64IM-NEXT: add a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = sdiv i32 %a, 5
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ret i32 %1
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}
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@ -164,6 +306,24 @@ define i32 @sdiv_pow2(i32 %a) nounwind {
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; RV32IM-NEXT: add a0, a0, a1
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; RV32IM-NEXT: srai a0, a0, 3
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: sdiv_pow2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: sext.w a1, a0
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; RV64I-NEXT: srli a1, a1, 60
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; RV64I-NEXT: andi a1, a1, 7
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: sraiw a0, a0, 3
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: sdiv_pow2:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: sext.w a1, a0
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; RV64IM-NEXT: srli a1, a1, 60
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; RV64IM-NEXT: andi a1, a1, 7
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; RV64IM-NEXT: add a0, a0, a1
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; RV64IM-NEXT: sraiw a0, a0, 3
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; RV64IM-NEXT: ret
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%1 = sdiv i32 %a, 8
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ret i32 %1
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}
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@ -186,6 +346,20 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind {
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: sdiv64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __divdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: sdiv64:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: div a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = sdiv i64 %a, %b
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ret i64 %1
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}
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@ -212,6 +386,83 @@ define i64 @sdiv64_constant(i64 %a) nounwind {
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; RV32IM-NEXT: lw ra, 12(sp)
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; RV32IM-NEXT: addi sp, sp, 16
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; RV32IM-NEXT: ret
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;
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; RV64I-LABEL: sdiv64_constant:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: addi a1, zero, 5
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; RV64I-NEXT: call __divdi3
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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;
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; RV64IM-LABEL: sdiv64_constant:
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; RV64IM: # %bb.0:
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; RV64IM-NEXT: lui a1, 13107
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; RV64IM-NEXT: addiw a1, a1, 819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, 819
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; RV64IM-NEXT: slli a1, a1, 12
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; RV64IM-NEXT: addi a1, a1, 819
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; RV64IM-NEXT: slli a1, a1, 13
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; RV64IM-NEXT: addi a1, a1, 1639
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; RV64IM-NEXT: mulh a0, a0, a1
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; RV64IM-NEXT: srli a1, a0, 63
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; RV64IM-NEXT: srai a0, a0, 1
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; RV64IM-NEXT: add a0, a0, a1
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; RV64IM-NEXT: ret
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%1 = sdiv i64 %a, 5
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ret i64 %1
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}
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||||
; Although this sdiv has two sexti32 operands, it shouldn't compile to divw on
|
||||
; RV64M as that wouldn't produce the correct result for e.g. INT_MIN/-1.
|
||||
|
||||
define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind {
|
||||
; RV32I-LABEL: sdiv64_sext_operands:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
; RV32I-NEXT: sw ra, 12(sp)
|
||||
; RV32I-NEXT: mv a2, a1
|
||||
; RV32I-NEXT: srai a1, a0, 31
|
||||
; RV32I-NEXT: srai a3, a2, 31
|
||||
; RV32I-NEXT: call __divdi3
|
||||
; RV32I-NEXT: lw ra, 12(sp)
|
||||
; RV32I-NEXT: addi sp, sp, 16
|
||||
; RV32I-NEXT: ret
|
||||
;
|
||||
; RV32IM-LABEL: sdiv64_sext_operands:
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: addi sp, sp, -16
|
||||
; RV32IM-NEXT: sw ra, 12(sp)
|
||||
; RV32IM-NEXT: mv a2, a1
|
||||
; RV32IM-NEXT: srai a1, a0, 31
|
||||
; RV32IM-NEXT: srai a3, a2, 31
|
||||
; RV32IM-NEXT: call __divdi3
|
||||
; RV32IM-NEXT: lw ra, 12(sp)
|
||||
; RV32IM-NEXT: addi sp, sp, 16
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: sdiv64_sext_operands:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: sext.w a0, a0
|
||||
; RV64I-NEXT: sext.w a1, a1
|
||||
; RV64I-NEXT: call __divdi3
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: sdiv64_sext_operands:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: sext.w a1, a1
|
||||
; RV64IM-NEXT: sext.w a0, a0
|
||||
; RV64IM-NEXT: div a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = sext i32 %b to i64
|
||||
%3 = sdiv i64 %1, %2
|
||||
ret i64 %3
|
||||
}
|
||||
|
||||
@ -3,8 +3,12 @@
|
||||
; RUN: | FileCheck -check-prefix=RV32I %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV32IM %s
|
||||
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64I %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64IM %s
|
||||
|
||||
define i32 @square(i32 %a) nounwind {
|
||||
define signext i32 @square(i32 %a) nounwind {
|
||||
; RV32I-LABEL: square:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
@ -19,11 +23,27 @@ define i32 @square(i32 %a) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: mul a0, a0, a0
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: square:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: mv a1, a0
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: sext.w a0, a0
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: square:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: mulw a0, a0, a0
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = mul i32 %a, %a
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mul(i32 %a, i32 %b) nounwind {
|
||||
define signext i32 @mul(i32 %a, i32 %b) nounwind {
|
||||
; RV32I-LABEL: mul:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
@ -37,11 +57,26 @@ define i32 @mul(i32 %a, i32 %b) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: mul a0, a0, a1
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mul:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: sext.w a0, a0
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mul:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: mulw a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = mul i32 %a, %b
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
define i32 @mul_constant(i32 %a) nounwind {
|
||||
define signext i32 @mul_constant(i32 %a) nounwind {
|
||||
; RV32I-LABEL: mul_constant:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
@ -57,6 +92,23 @@ define i32 @mul_constant(i32 %a) nounwind {
|
||||
; RV32IM-NEXT: addi a1, zero, 5
|
||||
; RV32IM-NEXT: mul a0, a0, a1
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mul_constant:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: addi a1, zero, 5
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: sext.w a0, a0
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mul_constant:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: addi a1, zero, 5
|
||||
; RV64IM-NEXT: mulw a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = mul i32 %a, 5
|
||||
ret i32 %1
|
||||
}
|
||||
@ -71,6 +123,16 @@ define i32 @mul_pow2(i32 %a) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: slli a0, a0, 3
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mul_pow2:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: slli a0, a0, 3
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mul_pow2:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: slli a0, a0, 3
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = mul i32 %a, 8
|
||||
ret i32 %1
|
||||
}
|
||||
@ -94,6 +156,20 @@ define i64 @mul64(i64 %a, i64 %b) nounwind {
|
||||
; RV32IM-NEXT: add a1, a3, a1
|
||||
; RV32IM-NEXT: mul a0, a0, a2
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mul64:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mul64:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: mul a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = mul i64 %a, %b
|
||||
ret i64 %1
|
||||
}
|
||||
@ -118,6 +194,22 @@ define i64 @mul64_constant(i64 %a) nounwind {
|
||||
; RV32IM-NEXT: add a1, a3, a1
|
||||
; RV32IM-NEXT: mul a0, a0, a2
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mul64_constant:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: addi a1, zero, 5
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mul64_constant:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: addi a1, zero, 5
|
||||
; RV64IM-NEXT: mul a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = mul i64 %a, 5
|
||||
ret i64 %1
|
||||
}
|
||||
@ -140,6 +232,26 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: mulh a0, a0, a1
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mulhs:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: sext.w a0, a0
|
||||
; RV64I-NEXT: sext.w a1, a1
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: srli a0, a0, 32
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mulhs:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: sext.w a1, a1
|
||||
; RV64IM-NEXT: sext.w a0, a0
|
||||
; RV64IM-NEXT: mul a0, a0, a1
|
||||
; RV64IM-NEXT: srli a0, a0, 32
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = sext i32 %a to i64
|
||||
%2 = sext i32 %b to i64
|
||||
%3 = mul i64 %1, %2
|
||||
@ -148,7 +260,7 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind {
|
||||
ret i32 %5
|
||||
}
|
||||
|
||||
define i32 @mulhu(i32 %a, i32 %b) nounwind {
|
||||
define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
|
||||
; RV32I-LABEL: mulhu:
|
||||
; RV32I: # %bb.0:
|
||||
; RV32I-NEXT: addi sp, sp, -16
|
||||
@ -166,6 +278,22 @@ define i32 @mulhu(i32 %a, i32 %b) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: mulhu a0, a0, a1
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: mulhu:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: call __muldi3
|
||||
; RV64I-NEXT: srli a0, a0, 32
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: mulhu:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: mul a0, a0, a1
|
||||
; RV64IM-NEXT: srli a0, a0, 32
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = zext i32 %a to i64
|
||||
%2 = zext i32 %b to i64
|
||||
%3 = mul i64 %1, %2
|
||||
|
||||
@ -3,6 +3,10 @@
|
||||
; RUN: | FileCheck -check-prefix=RV32I %s
|
||||
; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV32IM %s
|
||||
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64I %s
|
||||
; RUN: llc -mtriple=riscv64 -mattr=+m -verify-machineinstrs < %s \
|
||||
; RUN: | FileCheck -check-prefix=RV64IM %s
|
||||
|
||||
define i32 @urem(i32 %a, i32 %b) nounwind {
|
||||
; RV32I-LABEL: urem:
|
||||
@ -18,6 +22,24 @@ define i32 @urem(i32 %a, i32 %b) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: remu a0, a0, a1
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: urem:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: slli a0, a0, 32
|
||||
; RV64I-NEXT: srli a0, a0, 32
|
||||
; RV64I-NEXT: slli a1, a1, 32
|
||||
; RV64I-NEXT: srli a1, a1, 32
|
||||
; RV64I-NEXT: call __umoddi3
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: urem:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: remuw a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = urem i32 %a, %b
|
||||
ret i32 %1
|
||||
}
|
||||
@ -36,6 +58,22 @@ define i32 @srem(i32 %a, i32 %b) nounwind {
|
||||
; RV32IM: # %bb.0:
|
||||
; RV32IM-NEXT: rem a0, a0, a1
|
||||
; RV32IM-NEXT: ret
|
||||
;
|
||||
; RV64I-LABEL: srem:
|
||||
; RV64I: # %bb.0:
|
||||
; RV64I-NEXT: addi sp, sp, -16
|
||||
; RV64I-NEXT: sd ra, 8(sp)
|
||||
; RV64I-NEXT: sext.w a0, a0
|
||||
; RV64I-NEXT: sext.w a1, a1
|
||||
; RV64I-NEXT: call __moddi3
|
||||
; RV64I-NEXT: ld ra, 8(sp)
|
||||
; RV64I-NEXT: addi sp, sp, 16
|
||||
; RV64I-NEXT: ret
|
||||
;
|
||||
; RV64IM-LABEL: srem:
|
||||
; RV64IM: # %bb.0:
|
||||
; RV64IM-NEXT: remw a0, a0, a1
|
||||
; RV64IM-NEXT: ret
|
||||
%1 = srem i32 %a, %b
|
||||
ret i32 %1
|
||||
}
|
||||
|
||||
1308
test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
Normal file
1308
test/CodeGen/RISCV/rv64m-exhaustive-w-insts.ll
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user