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Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
This commit is contained in:
Andrew Trick
parent
0984f4927e
commit
916e01c917
@ -155,9 +155,13 @@ public:
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/// in the itinerary.
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///
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unsigned getStageLatency(unsigned ItinClassIndx) const {
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// If the target doesn't provide itinerary information, use a
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// simple non-zero default value for all instructions.
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if (isEmpty())
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// If the target doesn't provide itinerary information, use a simple
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// non-zero default value for all instructions. Some target's provide a
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// dummy (Generic) itinerary which should be handled as if it's itinerary is
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// empty. We identify this by looking for a reference to stage zero (invalid
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// stage). This is different from beginStage == endState != 0, which could
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// be used for zero-latency pseudo ops.
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if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0)
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return 1;
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// Calculate the maximum completion time for any stage.
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@ -102,11 +102,11 @@ static cl::opt<unsigned> AvgIPC(
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#ifndef NDEBUG
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namespace {
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// For sched=list-ilp, Count the number of times each factor comes into play.
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enum { FactPressureDiff, FactRegUses, FactHeight, FactDepth, FactStatic,
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FactOther, NumFactors };
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enum { FactPressureDiff, FactRegUses, FactStall, FactHeight, FactDepth,
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FactStatic, FactOther, NumFactors };
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}
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static const char *FactorName[NumFactors] =
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{"PressureDiff", "RegUses", "Height", "Depth","Static", "Other"};
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{"PressureDiff", "RegUses", "Stall", "Height", "Depth","Static", "Other"};
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static int FactorCount[NumFactors];
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#endif //!NDEBUG
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@ -463,6 +463,13 @@ void ScheduleDAGRRList::AdvancePastStalls(SUnit *SU) {
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if (DisableSchedCycles)
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return;
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// FIXME: Nodes such as CopyFromReg probably should not advance the current
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// cycle. Otherwise, we can wrongly mask real stalls. If the non-machine node
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// has predecessors the cycle will be advanced when they are scheduled.
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// But given the crude nature of modeling latency though such nodes, we
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// currently need to treat these nodes like real instructions.
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// if (!SU->getNode() || !SU->getNode()->isMachineOpcode()) return;
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unsigned ReadyCycle = isBottomUp ? SU->getHeight() : SU->getDepth();
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// Bump CurCycle to account for latency. We assume the latency of other
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@ -533,6 +540,8 @@ void ScheduleDAGRRList::EmitNode(SUnit *SU) {
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}
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}
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static void resetVRegCycle(SUnit *SU);
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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@ -542,7 +551,8 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
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#ifndef NDEBUG
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if (CurCycle < SU->getHeight())
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DEBUG(dbgs() << " Height [" << SU->getHeight() << "] pipeline stall!\n");
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DEBUG(dbgs() << " Height [" << SU->getHeight()
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<< "] pipeline stall!\n");
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#endif
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// FIXME: Do not modify node height. It may interfere with
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@ -559,7 +569,7 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
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AvailableQueue->ScheduledNode(SU);
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// If HazardRec is disabled, and each inst counts as one cycle, then
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// advance CurCycle before ReleasePredecessors to avoid useles pushed to
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// advance CurCycle before ReleasePredecessors to avoid useless pushes to
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// PendingQueue for schedulers that implement HasReadyFilter.
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if (!HazardRec->isEnabled() && AvgIPC < 2)
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AdvanceToCycle(CurCycle + 1);
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@ -580,20 +590,25 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU) {
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}
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}
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resetVRegCycle(SU);
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SU->isScheduled = true;
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// Conditions under which the scheduler should eagerly advance the cycle:
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// (1) No available instructions
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// (2) All pipelines full, so available instructions must have hazards.
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//
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// If HazardRec is disabled, the cycle was advanced earlier.
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// If HazardRec is disabled, the cycle was pre-advanced before calling
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// ReleasePredecessors. In that case, IssueCount should remain 0.
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//
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// Check AvailableQueue after ReleasePredecessors in case of zero latency.
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if (HazardRec->isEnabled() || AvgIPC > 1) {
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if (SU->getNode() && SU->getNode()->isMachineOpcode())
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++IssueCount;
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if ((HazardRec->isEnabled() && HazardRec->atIssueLimit())
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|| (!HazardRec->isEnabled() && AvgIPC > 1 && IssueCount == AvgIPC)
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|| AvailableQueue->empty())
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|| (!HazardRec->isEnabled() && IssueCount == AvgIPC))
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AdvanceToCycle(CurCycle + 1);
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}
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}
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/// CapturePred - This does the opposite of ReleasePred. Since SU is being
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@ -1220,7 +1235,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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// priority. If it is not ready put it back. Schedule the node.
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Sequence.reserve(SUnits.size());
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while (!AvailableQueue->empty()) {
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DEBUG(dbgs() << "\n*** Examining Available\n";
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DEBUG(dbgs() << "\nExamining Available:\n";
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AvailableQueue->dump(this));
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// Pick the best node to schedule taking all constraints into
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@ -1661,17 +1676,6 @@ void RegReductionPQBase::CalculateSethiUllmanNumbers() {
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CalcNodeSethiUllmanNumber(&(*SUnits)[i], SethiUllmanNumbers);
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}
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void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
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SUnits = &sunits;
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// Add pseudo dependency edges for two-address nodes.
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AddPseudoTwoAddrDeps();
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// Reroute edges to nodes with multiple uses.
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if (!TracksRegPressure)
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PrescheduleNodesWithMultipleUses();
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// Calculate node priorities.
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CalculateSethiUllmanNumbers();
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}
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void RegReductionPQBase::addNode(const SUnit *SU) {
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unsigned SUSize = SethiUllmanNumbers.size();
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if (SUnits->size() > SUSize)
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@ -2008,7 +2012,29 @@ static unsigned calcMaxScratches(const SUnit *SU) {
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return Scratches;
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}
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/// hasOnlyLiveOutUse - Return true if SU has a single value successor that is a
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/// hasOnlyLiveInOpers - Return true if SU has only value predecessors that are
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/// CopyFromReg from a virtual register.
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static bool hasOnlyLiveInOpers(const SUnit *SU) {
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bool RetVal = false;
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl()) continue;
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const SUnit *PredSU = I->getSUnit();
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if (PredSU->getNode() &&
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PredSU->getNode()->getOpcode() == ISD::CopyFromReg) {
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unsigned Reg =
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cast<RegisterSDNode>(PredSU->getNode()->getOperand(1))->getReg();
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if (TargetRegisterInfo::isVirtualRegister(Reg)) {
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RetVal = true;
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continue;
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}
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}
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return false;
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}
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return RetVal;
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}
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/// hasOnlyLiveOutUses - Return true if SU has only value successors that are
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/// CopyToReg to a virtual register. This SU def is probably a liveout and
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/// it has no other use. It should be scheduled closer to the terminator.
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static bool hasOnlyLiveOutUses(const SUnit *SU) {
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@ -2030,62 +2056,71 @@ static bool hasOnlyLiveOutUses(const SUnit *SU) {
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return RetVal;
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}
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/// UnitsSharePred - Return true if the two scheduling units share a common
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/// data predecessor.
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static bool UnitsSharePred(const SUnit *left, const SUnit *right) {
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SmallSet<const SUnit*, 4> Preds;
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for (SUnit::const_pred_iterator I = left->Preds.begin(),E = left->Preds.end();
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I != E; ++I) {
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if (I->isCtrl()) continue; // ignore chain preds
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Preds.insert(I->getSUnit());
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}
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for (SUnit::const_pred_iterator I = right->Preds.begin(),E = right->Preds.end();
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I != E; ++I) {
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if (I->isCtrl()) continue; // ignore chain preds
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if (Preds.count(I->getSUnit()))
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return true;
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}
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return false;
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}
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// Return true if the virtual register defined by VRCycleSU may interfere with
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// VRUseSU.
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// Set isVRegCycle for a node with only live in opers and live out uses. Also
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// set isVRegCycle for its CopyFromReg operands.
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//
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// Note: We may consider two SU's that use the same value live into a loop as
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// interferng even though the value is not an induction variable. This is an
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// unfortunate consequence of scheduling on the selection DAG.
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static bool checkVRegCycleInterference(const SUnit *VRCycleSU,
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const SUnit *VRUseSU) {
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for (SUnit::const_pred_iterator I = VRCycleSU->Preds.begin(),
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E = VRCycleSU->Preds.end(); I != E; ++I) {
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// This is only relevant for single-block loops, in which case the VRegCycle
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// node is likely an induction variable in which the operand and target virtual
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// registers should be coalesced (e.g. pre/post increment values). Setting the
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// isVRegCycle flag helps the scheduler prioritize other uses of the same
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// CopyFromReg so that this node becomes the virtual register "kill". This
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// avoids interference between the values live in and out of the block and
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// eliminates a copy inside the loop.
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static void initVRegCycle(SUnit *SU) {
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if (DisableSchedVRegCycle)
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return;
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if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
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return;
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DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
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SU->isVRegCycle = true;
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for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl()) continue;
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I->getSUnit()->isVRegCycle = true;
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}
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}
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// After scheduling the definition of a VRegCycle, clear the isVRegCycle flag of
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// CopyFromReg operands. We should no longer penalize other uses of this VReg.
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static void resetVRegCycle(SUnit *SU) {
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if (!SU->isVRegCycle)
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return;
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for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl()) continue; // ignore chain preds
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SDNode *InNode = I->getSUnit()->getNode();
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if (!InNode || InNode->getOpcode() != ISD::CopyFromReg)
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continue;
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for (SUnit::const_pred_iterator II = VRUseSU->Preds.begin(),
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EE = VRUseSU->Preds.end(); II != EE; ++II) {
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if (II->getSUnit() == I->getSUnit())
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SUnit *PredSU = I->getSUnit();
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if (PredSU->isVRegCycle) {
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assert(PredSU->getNode()->getOpcode() == ISD::CopyFromReg &&
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"VRegCycle def must be CopyFromReg");
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I->getSUnit()->isVRegCycle = 0;
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}
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}
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}
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// Return true if this SUnit uses a CopyFromReg node marked as a VRegCycle. This
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// means a node that defines the VRegCycle has not been scheduled yet.
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static bool hasVRegCycleUse(const SUnit *SU) {
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// If this SU also defines the VReg, don't hoist it as a "use".
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if (SU->isVRegCycle)
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return false;
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for (SUnit::const_pred_iterator I = SU->Preds.begin(),E = SU->Preds.end();
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I != E; ++I) {
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if (I->isCtrl()) continue; // ignore chain preds
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if (I->getSUnit()->isVRegCycle &&
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I->getSUnit()->getNode()->getOpcode() == ISD::CopyFromReg) {
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DEBUG(dbgs() << " VReg cycle use: SU (" << SU->NodeNum << ")\n");
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return true;
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}
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}
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return false;
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}
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// Compare the VRegCycle properties of the nodes.
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// Return -1 if left has higher priority, 1 if right has higher priority.
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// Return 0 if priority is equivalent.
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static int BUCompareVRegCycle(const SUnit *left, const SUnit *right) {
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if (left->isVRegCycle && !right->isVRegCycle) {
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if (checkVRegCycleInterference(left, right))
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return -1;
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}
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else if (!left->isVRegCycle && right->isVRegCycle) {
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if (checkVRegCycleInterference(right, left))
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return 1;
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}
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return 0;
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}
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// Check for either a dependence (latency) or resource (hazard) stall.
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//
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// Note: The ScheduleHazardRecognizer interface requires a non-const SU.
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@ -2101,23 +2136,12 @@ static bool BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) {
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// Return 0 if latency-based priority is equivalent.
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static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
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RegReductionPQBase *SPQ) {
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// If the two nodes share an operand and one of them has a single
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// use that is a live out copy, favor the one that is live out. Otherwise
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// it will be difficult to eliminate the copy if the instruction is a
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// loop induction variable update. e.g.
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// BB:
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// sub r1, r3, #1
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// str r0, [r2, r3]
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// mov r3, r1
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// cmp
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// bne BB
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bool SharePred = UnitsSharePred(left, right);
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// FIXME: Only adjust if BB is a loop back edge.
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// FIXME: What's the cost of a copy?
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int LBonus = (SharePred && hasOnlyLiveOutUses(left)) ? 1 : 0;
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int RBonus = (SharePred && hasOnlyLiveOutUses(right)) ? 1 : 0;
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int LHeight = (int)left->getHeight() - LBonus;
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int RHeight = (int)right->getHeight() - RBonus;
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// Scheduling an instruction that uses a VReg whose postincrement has not yet
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// been scheduled will induce a copy. Model this as an extra cycle of latency.
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int LPenalty = hasVRegCycleUse(left) ? 1 : 0;
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int RPenalty = hasVRegCycleUse(right) ? 1 : 0;
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int LHeight = (int)left->getHeight() + LPenalty;
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int RHeight = (int)right->getHeight() + RPenalty;
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bool LStall = (!checkPref || left->SchedulingPref == Sched::Latency) &&
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BUHasStall(left, LHeight, SPQ);
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@ -2128,37 +2152,48 @@ static int BUCompareLatency(SUnit *left, SUnit *right, bool checkPref,
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// If scheduling either one of the node will cause a pipeline stall, sort
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// them according to their height.
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if (LStall) {
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if (!RStall)
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if (!RStall) {
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DEBUG(++FactorCount[FactStall]);
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return 1;
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if (LHeight != RHeight)
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}
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if (LHeight != RHeight) {
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DEBUG(++FactorCount[FactStall]);
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return LHeight > RHeight ? 1 : -1;
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} else if (RStall)
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}
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} else if (RStall) {
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DEBUG(++FactorCount[FactStall]);
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return -1;
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}
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// If either node is scheduling for latency, sort them by height/depth
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// and latency.
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if (!checkPref || (left->SchedulingPref == Sched::Latency ||
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right->SchedulingPref == Sched::Latency)) {
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if (DisableSchedCycles) {
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if (LHeight != RHeight)
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if (LHeight != RHeight) {
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DEBUG(++FactorCount[FactHeight]);
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return LHeight > RHeight ? 1 : -1;
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}
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}
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else {
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// If neither instruction stalls (!LStall && !RStall) then
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// its height is already covered so only its depth matters. We also reach
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// this if both stall but have the same height.
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unsigned LDepth = left->getDepth();
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unsigned RDepth = right->getDepth();
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int LDepth = left->getDepth() - LPenalty;
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int RDepth = right->getDepth() - RPenalty;
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if (LDepth != RDepth) {
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DEBUG(++FactorCount[FactDepth]);
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DEBUG(dbgs() << " Comparing latency of SU (" << left->NodeNum
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<< ") depth " << LDepth << " vs SU (" << right->NodeNum
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<< ") depth " << RDepth << "\n");
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return LDepth < RDepth ? 1 : -1;
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}
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}
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if (left->Latency != right->Latency)
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if (left->Latency != right->Latency) {
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DEBUG(++FactorCount[FactOther]);
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return left->Latency > right->Latency ? 1 : -1;
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}
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}
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return 0;
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}
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@ -2169,7 +2204,19 @@ static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
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DEBUG(++FactorCount[FactStatic]);
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return LPriority > RPriority;
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}
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DEBUG(++FactorCount[FactOther]);
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else if(LPriority == 0) {
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// Schedule zero-latency TokenFactor below any other special
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// nodes. The alternative may be to avoid artificially boosting the
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// TokenFactor's height when it is scheduled, but we currently rely on an
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// instruction's final height to equal the cycle in which it is scheduled,
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// so heights are monotonically increasing.
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unsigned LOpc = left->getNode() ? left->getNode()->getOpcode() : 0;
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unsigned ROpc = right->getNode() ? right->getNode()->getOpcode() : 0;
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if (LOpc == ISD::TokenFactor)
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return false;
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if (ROpc == ISD::TokenFactor)
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return true;
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}
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// Try schedule def + use closer when Sethi-Ullman numbers are the same.
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// e.g.
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@ -2190,14 +2237,18 @@ static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
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// This creates more short live intervals.
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unsigned LDist = closestSucc(left);
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unsigned RDist = closestSucc(right);
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if (LDist != RDist)
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if (LDist != RDist) {
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DEBUG(++FactorCount[FactOther]);
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return LDist < RDist;
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}
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// How many registers becomes live when the node is scheduled.
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unsigned LScratch = calcMaxScratches(left);
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unsigned RScratch = calcMaxScratches(right);
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if (LScratch != RScratch)
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if (LScratch != RScratch) {
|
||||
DEBUG(++FactorCount[FactOther]);
|
||||
return LScratch > RScratch;
|
||||
}
|
||||
|
||||
if (!DisableSchedCycles) {
|
||||
int result = BUCompareLatency(left, right, false /*checkPref*/, SPQ);
|
||||
@ -2205,15 +2256,20 @@ static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
|
||||
return result > 0;
|
||||
}
|
||||
else {
|
||||
if (left->getHeight() != right->getHeight())
|
||||
if (left->getHeight() != right->getHeight()) {
|
||||
DEBUG(++FactorCount[FactHeight]);
|
||||
return left->getHeight() > right->getHeight();
|
||||
}
|
||||
|
||||
if (left->getDepth() != right->getDepth())
|
||||
if (left->getDepth() != right->getDepth()) {
|
||||
DEBUG(++FactorCount[FactDepth]);
|
||||
return left->getDepth() < right->getDepth();
|
||||
}
|
||||
}
|
||||
|
||||
assert(left->NodeQueueId && right->NodeQueueId &&
|
||||
"NodeQueueId cannot be zero");
|
||||
DEBUG(++FactorCount[FactOther]);
|
||||
return (left->NodeQueueId > right->NodeQueueId);
|
||||
}
|
||||
|
||||
@ -2264,24 +2320,22 @@ bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
|
||||
// Avoid causing spills. If register pressure is high, schedule for
|
||||
// register pressure reduction.
|
||||
if (LHigh && !RHigh) {
|
||||
DEBUG(++FactorCount[FactPressureDiff]);
|
||||
DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
|
||||
<< right->NodeNum << ")\n");
|
||||
return true;
|
||||
}
|
||||
else if (!LHigh && RHigh) {
|
||||
DEBUG(++FactorCount[FactPressureDiff]);
|
||||
DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
|
||||
<< left->NodeNum << ")\n");
|
||||
return false;
|
||||
}
|
||||
int result = 0;
|
||||
if (!DisableSchedVRegCycle) {
|
||||
result = BUCompareVRegCycle(left, right);
|
||||
}
|
||||
if (result == 0 && !LHigh && !RHigh) {
|
||||
result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
|
||||
}
|
||||
if (!LHigh && !RHigh) {
|
||||
int result = BUCompareLatency(left, right, true /*checkPref*/, SPQ);
|
||||
if (result != 0)
|
||||
return result > 0;
|
||||
}
|
||||
return BURRSort(left, right, SPQ);
|
||||
}
|
||||
|
||||
@ -2347,12 +2401,6 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
|
||||
if (RReduce && !LReduce) return true;
|
||||
}
|
||||
|
||||
if (!DisableSchedVRegCycle) {
|
||||
int result = BUCompareVRegCycle(left, right);
|
||||
if (result != 0)
|
||||
return result > 0;
|
||||
}
|
||||
|
||||
if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
|
||||
DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
|
||||
<< " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
|
||||
@ -2391,6 +2439,24 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
|
||||
return BURRSort(left, right, SPQ);
|
||||
}
|
||||
|
||||
void RegReductionPQBase::initNodes(std::vector<SUnit> &sunits) {
|
||||
SUnits = &sunits;
|
||||
// Add pseudo dependency edges for two-address nodes.
|
||||
AddPseudoTwoAddrDeps();
|
||||
// Reroute edges to nodes with multiple uses.
|
||||
if (!TracksRegPressure)
|
||||
PrescheduleNodesWithMultipleUses();
|
||||
// Calculate node priorities.
|
||||
CalculateSethiUllmanNumbers();
|
||||
|
||||
// For single block loops, mark nodes that look like canonical IV increments.
|
||||
if (scheduleDAG->BB->isSuccessor(scheduleDAG->BB)) {
|
||||
for (unsigned i = 0, e = sunits.size(); i != e; ++i) {
|
||||
initVRegCycle(&sunits[i]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Preschedule for Register Pressure
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -342,10 +342,6 @@ void ScheduleDAGSDNodes::BuildSchedUnits() {
|
||||
assert(N->getNodeId() == -1 && "Node already inserted!");
|
||||
N->setNodeId(NodeSUnit->NodeNum);
|
||||
|
||||
// Set isVRegCycle if the node operands are live into and value is live out
|
||||
// of a single block loop.
|
||||
InitVRegCycleFlag(NodeSUnit);
|
||||
|
||||
// Compute NumRegDefsLeft. This must be done before AddSchedEdges.
|
||||
InitNumRegDefsLeft(NodeSUnit);
|
||||
|
||||
@ -417,6 +413,10 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
|
||||
|
||||
// If this is a ctrl dep, latency is 1.
|
||||
unsigned OpLatency = isChain ? 1 : OpSU->Latency;
|
||||
// Special-case TokenFactor chains as zero-latency.
|
||||
if(isChain && OpN->getOpcode() == ISD::TokenFactor)
|
||||
OpLatency = 0;
|
||||
|
||||
const SDep &dep = SDep(OpSU, isChain ? SDep::Order : SDep::Data,
|
||||
OpLatency, PhysReg);
|
||||
if (!isChain && !UnitLatencies) {
|
||||
@ -512,47 +512,6 @@ void ScheduleDAGSDNodes::RegDefIter::Advance() {
|
||||
}
|
||||
}
|
||||
|
||||
// Set isVRegCycle if this node's single use is CopyToReg and its only active
|
||||
// data operands are CopyFromReg.
|
||||
//
|
||||
// This is only relevant for single-block loops, in which case the VRegCycle
|
||||
// node is likely an induction variable in which the operand and target virtual
|
||||
// registers should be coalesced (e.g. pre/post increment values). Setting the
|
||||
// isVRegCycle flag helps the scheduler prioritize other uses of the same
|
||||
// CopyFromReg so that this node becomes the virtual register "kill". This
|
||||
// avoids interference between the values live in and out of the block and
|
||||
// eliminates a copy inside the loop.
|
||||
void ScheduleDAGSDNodes::InitVRegCycleFlag(SUnit *SU) {
|
||||
if (!BB->isSuccessor(BB))
|
||||
return;
|
||||
|
||||
SDNode *N = SU->getNode();
|
||||
if (N->getGluedNode())
|
||||
return;
|
||||
|
||||
if (!N->hasOneUse() || N->use_begin()->getOpcode() != ISD::CopyToReg)
|
||||
return;
|
||||
|
||||
bool FoundLiveIn = false;
|
||||
for (SDNode::op_iterator OI = N->op_begin(), E = N->op_end(); OI != E; ++OI) {
|
||||
EVT OpVT = OI->getValueType();
|
||||
assert(OpVT != MVT::Glue && "Glued nodes should be in same sunit!");
|
||||
|
||||
if (OpVT == MVT::Other)
|
||||
continue; // ignore chain operands
|
||||
|
||||
if (isPassiveNode(OI->getNode()))
|
||||
continue; // ignore constants and such
|
||||
|
||||
if (OI->getNode()->getOpcode() != ISD::CopyFromReg)
|
||||
return;
|
||||
|
||||
FoundLiveIn = true;
|
||||
}
|
||||
if (FoundLiveIn)
|
||||
SU->isVRegCycle = true;
|
||||
}
|
||||
|
||||
void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
|
||||
assert(SU->NumRegDefsLeft == 0 && "expect a new node");
|
||||
for (RegDefIter I(SU, this); I.IsValid(); I.Advance()) {
|
||||
@ -562,6 +521,16 @@ void ScheduleDAGSDNodes::InitNumRegDefsLeft(SUnit *SU) {
|
||||
}
|
||||
|
||||
void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
|
||||
SDNode *N = SU->getNode();
|
||||
|
||||
// TokenFactor operands are considered zero latency, and some schedulers
|
||||
// (e.g. Top-Down list) may rely on the fact that operand latency is nonzero
|
||||
// whenever node latency is nonzero.
|
||||
if (N && N->getOpcode() == ISD::TokenFactor) {
|
||||
SU->Latency = 0;
|
||||
return;
|
||||
}
|
||||
|
||||
// Check to see if the scheduler cares about latencies.
|
||||
if (ForceUnitLatencies()) {
|
||||
SU->Latency = 1;
|
||||
@ -569,7 +538,6 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) {
|
||||
}
|
||||
|
||||
if (!InstrItins || InstrItins->isEmpty()) {
|
||||
SDNode *N = SU->getNode();
|
||||
if (N && N->isMachineOpcode() &&
|
||||
TII->isHighLatencyDef(N->getMachineOpcode()))
|
||||
SU->Latency = HighLatencyCycles;
|
||||
|
||||
@ -1,10 +1,8 @@
|
||||
; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic -disable-post-ra | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s
|
||||
|
||||
; The ARM magic hinting works best with linear scan.
|
||||
; CHECK: ldmia
|
||||
; CHECK: stmia
|
||||
; CHECK: ldrh
|
||||
; CHECK: ldrd
|
||||
; CHECK: strd
|
||||
; CHECK: ldrb
|
||||
|
||||
%struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 }
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
|
||||
; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source | FileCheck %s
|
||||
|
||||
define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
|
||||
;CHECK: vrecpe.f32
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
|
||||
; Test that we correctly align elements when using va_arg
|
||||
|
||||
; CHECK: test1:
|
||||
; CHECK-NOT: bfc
|
||||
; CHECK: add r0, r0, #7
|
||||
; CHECK: bfc r0, #0, #3
|
||||
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
|
||||
; CHECK: bfc [[REG]], #0, #3
|
||||
; CHECK-NOT: bfc
|
||||
|
||||
define i64 @test1(i32 %i, ...) nounwind optsize {
|
||||
@ -19,8 +19,8 @@ entry:
|
||||
|
||||
; CHECK: test2:
|
||||
; CHECK-NOT: bfc
|
||||
; CHECK: add r0, r0, #7
|
||||
; CHECK: bfc r0, #0, #3
|
||||
; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
|
||||
; CHECK: bfc [[REG]], #0, #3
|
||||
; CHECK-NOT: bfc
|
||||
; CHECK: bx lr
|
||||
|
||||
|
||||
@ -40,8 +40,8 @@ define void @test_add(float* %P, double* %D) {
|
||||
define void @test_ext_round(float* %P, double* %D) {
|
||||
;CHECK: test_ext_round:
|
||||
%a = load float* %P ; <float> [#uses=1]
|
||||
;CHECK: vcvt.f32.f64
|
||||
;CHECK: vcvt.f64.f32
|
||||
;CHECK: vcvt.f32.f64
|
||||
%b = fpext float %a to double ; <double> [#uses=1]
|
||||
%A = load double* %D ; <double> [#uses=1]
|
||||
%B = fptrunc double %A to float ; <float> [#uses=1]
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s
|
||||
; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
|
||||
; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s -regalloc=basic | FileCheck %s
|
||||
|
||||
|
||||
; All test functions do the same thing - they return the first variable
|
||||
@ -31,9 +31,9 @@ entry:
|
||||
|
||||
; CHECK: va1:
|
||||
; CHECK: addiu $sp, $sp, -32
|
||||
; CHECK: sw $5, 36($sp)
|
||||
; CHECK: sw $6, 40($sp)
|
||||
; CHECK: sw $7, 44($sp)
|
||||
; CHECK: sw $6, 40($sp)
|
||||
; CHECK: sw $5, 36($sp)
|
||||
; CHECK: lw $2, 36($sp)
|
||||
}
|
||||
|
||||
@ -57,10 +57,10 @@ entry:
|
||||
|
||||
; CHECK: va2:
|
||||
; CHECK: addiu $sp, $sp, -40
|
||||
; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
|
||||
; CHECK: sw $5, 44($sp)
|
||||
; CHECK: sw $6, 48($sp)
|
||||
; CHECK: sw $7, 52($sp)
|
||||
; CHECK: sw $6, 48($sp)
|
||||
; CHECK: sw $5, 44($sp)
|
||||
; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
|
||||
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
|
||||
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
|
||||
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
|
||||
@ -85,8 +85,8 @@ entry:
|
||||
|
||||
; CHECK: va3:
|
||||
; CHECK: addiu $sp, $sp, -40
|
||||
; CHECK: sw $6, 48($sp)
|
||||
; CHECK: sw $7, 52($sp)
|
||||
; CHECK: sw $6, 48($sp)
|
||||
; CHECK: lw $2, 48($sp)
|
||||
}
|
||||
|
||||
@ -108,8 +108,8 @@ entry:
|
||||
|
||||
; CHECK: va4:
|
||||
; CHECK: addiu $sp, $sp, -48
|
||||
; CHECK: sw $6, 56($sp)
|
||||
; CHECK: sw $7, 60($sp)
|
||||
; CHECK: sw $6, 56($sp)
|
||||
; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
|
||||
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
|
||||
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
|
||||
|
||||
@ -128,9 +128,9 @@ define i32 @test10(i32 %p0) {
|
||||
|
||||
; ARMv7M: test10
|
||||
; ARMv7M: mov.w r1, #16253176
|
||||
; ARMv7M: mov.w r2, #458759
|
||||
; ARMv7M: and.w r0, r1, r0, lsr #7
|
||||
; ARMv7M: mov.w r1, #458759
|
||||
; ARMv7M: and.w r1, r1, r0, lsr #5
|
||||
; ARMv7M: and.w r1, r2, r0, lsr #5
|
||||
; ARMv7M: orrs r0, r1
|
||||
%tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1]
|
||||
%tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user