RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

We also need to keep the operand index for two address check.

Browse Source 
llvm-svn: 59562
This commit is contained in:
Evan Cheng 2008-11-18 22:56:19 +00:00
parent 145b3db050
commit 91d6c38321
1 changed files with 11 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/CodeGen/RegisterScavenging.cpp
View File

@ -193,25 +193,25 @@ void RegScavenger::forward() {
bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF; bool IsImpDef = MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF;
// Separate register operands into 3 classes: uses, defs, earlyclobbers. // Separate register operands into 3 classes: uses, defs, earlyclobbers.
SmallVector<const MachineOperand*, 4> UseMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> UseMOs;
SmallVector<const MachineOperand*, 4> DefMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> DefMOs;
SmallVector<const MachineOperand*, 4> EarlyClobberMOs; SmallVector<std::pair<const MachineOperand*,unsigned>, 4> EarlyClobberMOs;
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i); const MachineOperand &MO = MI->getOperand(i);
if (!MO.isReg() || MO.getReg() == 0) if (!MO.isReg() || MO.getReg() == 0)
continue; continue;
if (MO.isUse()) if (MO.isUse())
UseMOs.push_back(&MO); UseMOs.push_back(std::make_pair(&MO,i));
else if (MO.isEarlyClobber()) else if (MO.isEarlyClobber())
EarlyClobberMOs.push_back(&MO); EarlyClobberMOs.push_back(std::make_pair(&MO,i));
else else
DefMOs.push_back(&MO); DefMOs.push_back(std::make_pair(&MO,i));
} }
// Process uses first. // Process uses first.
BitVector UseRegs(NumPhysRegs); BitVector UseRegs(NumPhysRegs);
for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) { for (unsigned i = 0, e = UseMOs.size(); i != e; ++i) {
const MachineOperand &MO = *UseMOs[i]; const MachineOperand MO = *UseMOs[i].first;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
if (!isUsed(Reg)) { if (!isUsed(Reg)) {
@ -244,7 +244,9 @@ void RegScavenger::forward() {
for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) { for (unsigned i = 0, e = NumECs + NumDefs; i != e; ++i) {
const MachineOperand &MO = (i < NumECs) const MachineOperand &MO = (i < NumECs)
? *EarlyClobberMOs[i] : *DefMOs[i-NumECs]; ? *EarlyClobberMOs[i].first : *DefMOs[i-NumECs].first;
unsigned Idx = (i < NumECs)
? EarlyClobberMOs[i].second : DefMOs[i-NumECs].second;
unsigned Reg = MO.getReg(); unsigned Reg = MO.getReg();
// If it's dead upon def, then it is now free. // If it's dead upon def, then it is now free.
@ -254,7 +256,7 @@ void RegScavenger::forward() {
} }
// Skip two-address destination operand. // Skip two-address destination operand.
if (TID.findTiedToSrcOperand(i) != -1) { if (TID.findTiedToSrcOperand(Idx) != -1) {
assert(isUsed(Reg) && "Using an undefined register!"); assert(isUsed(Reg) && "Using an undefined register!");
continue; continue;
} }