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https://github.com/RPCS3/llvm-mirror.git
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[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Differential Revision: https://reviews.llvm.org/D19906 llvm-svn: 276397
This commit is contained in:
Hrvoje Varga
parent
565efe666f
commit
91d7fa7411
@ -236,6 +236,7 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) {
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// beq $r0, $zero, $L2 => beqz $r0, $L2
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return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS);
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case Mips::BNE:
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case Mips::BNE_MM:
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// bne $r0, $zero, $L2 => bnez $r0, $L2
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return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS);
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case Mips::BNE64:
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@ -1047,6 +1047,15 @@ def : MipsPat<(atomic_load_16 addr:$a),
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def : MipsPat<(i32 (extloadi16 addr:$src)),
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(LHu_MM addr:$src)>;
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defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
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SLTiu_MM, ZERO>;
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defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
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defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
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defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
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defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
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defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>;
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//===----------------------------------------------------------------------===//
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// MicroMips instruction aliases
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//===----------------------------------------------------------------------===//
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@ -1080,6 +1089,12 @@ let Predicates = [InMicroMips] in {
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(TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"tne $rs, $rt",
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(TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
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def : MipsInstAlias<"slt $rs, $rt, $imm",
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(SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
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simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<"sltu $rs, $rt, $imm",
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(SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt,
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simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<"sll $rd, $rt, $rs",
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(SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
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def : MipsInstAlias<"sra $rd, $rt, $rs",
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@ -1115,4 +1130,8 @@ let Predicates = [InMicroMips] in {
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(XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
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def : MipsInstAlias<"not $rt, $rs",
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(NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
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def : MipsInstAlias<"bnez $rs,$offset",
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(BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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def : MipsInstAlias<"beqz $rs,$offset",
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(BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
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}
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@ -537,21 +537,21 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
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}
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defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
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defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
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ZERO_64>;
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def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
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(BLEZ64 i64:$lhs, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
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(BGEZ64 i64:$lhs, bb:$dst)>;
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// setcc patterns
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defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<GPR64, SLT64, SLTu64>;
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defm : SetgtPats<GPR64, SLT64, SLTu64>;
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defm : SetgePats<GPR64, SLT64, SLTu64>;
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defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
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let AdditionalPredicates = [NotInMicroMips] in {
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defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<GPR64, XORi, SLT64, SLTu64>;
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defm : SetgtPats<GPR64, SLT64, SLTu64>;
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defm : SetgePats<GPR64, XORi, SLT64, SLTu64>;
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defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>;
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}
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// truncate
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def : MipsPat<(trunc (assertsext GPR64:$src)),
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(EXTRACT_SUBREG GPR64:$src, sub_32)>;
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@ -269,7 +269,9 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
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if (Subtarget.inMicroMipsMode()) {
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switch (Opcode) {
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case Mips::BNE:
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case Mips::BNE_MM:
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case Mips::BEQ:
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case Mips::BEQ_MM:
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// microMIPS has NE,EQ branches that do not have delay slots provided one
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// of the operands is zero.
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if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
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@ -302,12 +304,14 @@ unsigned MipsInstrInfo::getEquivalentCompactForm(
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case Mips::BAL:
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return Mips::BALC;
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case Mips::BEQ:
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case Mips::BEQ_MM:
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if (canUseShortMicroMipsCTI)
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return Mips::BEQZC_MM;
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else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
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return 0;
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return Mips::BEQC;
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case Mips::BNE:
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case Mips::BNE_MM:
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if (canUseShortMicroMipsCTI)
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return Mips::BNEZC_MM;
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else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
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@ -1686,33 +1686,35 @@ let AdditionalPredicates = [NotInMicroMips] in {
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}
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def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>,
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ISA_MIPS1_NOT_32R6_64R6;
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def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM<0xa>;
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def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM<0xb>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM<0xa>;
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def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
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SLTI_FM<0xb>;
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}
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def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM;
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let AdditionalPredicates = [NotInMicroMips] in {
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
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ADD_FM<0, 0x21>;
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def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
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ADD_FM<0, 0x23>;
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/// Arithmetic Instructions (3-Operand, R-Type)
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def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
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ADD_FM<0, 0x21>;
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def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
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ADD_FM<0, 0x23>;
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}
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let Defs = [HI0, LO0] in
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def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
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ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
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def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>;
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def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>;
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def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
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def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
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ADD_FM<0, 0x24>;
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def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
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ADD_FM<0, 0x25>;
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def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
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ADD_FM<0, 0x26>;
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def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
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def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
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def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
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def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
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ADD_FM<0, 0x24>;
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def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
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ADD_FM<0, 0x25>;
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def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
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ADD_FM<0, 0x26>;
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def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
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}
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/// Shift Instructions
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@ -2223,13 +2225,13 @@ def : MipsInstAlias<"negu $rt",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
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def : MipsInstAlias<"negu $rt, $rs",
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(SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
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def : MipsInstAlias<
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<
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"slt $rs, $rt, $imm",
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(SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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def : MipsInstAlias<
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def : MipsInstAlias<
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"sltu $rt, $rs, $imm",
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(SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>;
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let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<
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"and $rs, $rt, $imm",
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(ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>;
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@ -2558,38 +2560,39 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
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// brcond patterns
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multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
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Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
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Instruction SLTiuOp, Register ZEROReg> {
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multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1,
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Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp,
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Instruction SLTiOp, Instruction SLTiuOp,
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Register ZEROReg> {
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def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
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(BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
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def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
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(BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
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(BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
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(BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
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(BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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(BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
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(BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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(BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
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(BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
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(BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
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(BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
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(BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
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(BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
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(BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
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(BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
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def : MipsPat<(brcond RC:$cond, bb:$dst),
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(BNEOp RC:$cond, ZEROReg, bb:$dst)>;
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}
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defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
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let AdditionalPredicates = [NotInMicroMips] in {
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defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
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}
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def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
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(BLEZ i32:$lhs, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
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@ -2608,11 +2611,12 @@ multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
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(SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
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}
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multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
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multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,
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Instruction SLTuOp> {
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def : MipsPat<(setle RC:$lhs, RC:$rhs),
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(XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
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(XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>;
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def : MipsPat<(setule RC:$lhs, RC:$rhs),
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(XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
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(XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>;
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}
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multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
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@ -2622,26 +2626,29 @@ multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
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(SLTuOp RC:$rhs, RC:$lhs)>;
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}
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multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
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multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp,
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Instruction SLTuOp> {
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def : MipsPat<(setge RC:$lhs, RC:$rhs),
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(XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
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(XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>;
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def : MipsPat<(setuge RC:$lhs, RC:$rhs),
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(XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
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(XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>;
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}
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multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
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Instruction SLTiuOp> {
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multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp,
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Instruction SLTiOp, Instruction SLTiuOp> {
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def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
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(XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
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(XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
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def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
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(XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
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(XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
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}
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defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
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defm : SetlePats<GPR32, SLT, SLTu>;
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defm : SetgtPats<GPR32, SLT, SLTu>;
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defm : SetgePats<GPR32, SLT, SLTu>;
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defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
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let AdditionalPredicates = [NotInMicroMips] in {
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defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
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defm : SetlePats<GPR32, XORi, SLT, SLTu>;
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defm : SetgtPats<GPR32, SLT, SLTu>;
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defm : SetgePats<GPR32, XORi, SLT, SLTu>;
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defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>;
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}
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// bswap pattern
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def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
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@ -408,7 +408,9 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BEQ: return Mips::BNE;
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case Mips::BEQ_MM: return Mips::BNE_MM;
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case Mips::BNE: return Mips::BEQ;
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case Mips::BNE_MM: return Mips::BEQ_MM;
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case Mips::BGTZ: return Mips::BLEZ;
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||||
case Mips::BGEZ: return Mips::BLTZ;
|
||||
case Mips::BLTZ: return Mips::BGEZ;
|
||||
@ -506,16 +508,17 @@ unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
|
||||
return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ ||
|
||||
Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ ||
|
||||
Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 ||
|
||||
Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
|
||||
Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B ||
|
||||
Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM ||
|
||||
Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC ||
|
||||
Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC ||
|
||||
Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC ||
|
||||
Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC ||
|
||||
return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
|
||||
Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
|
||||
Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
|
||||
Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
|
||||
Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
|
||||
Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
|
||||
Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
|
||||
Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC ||
|
||||
Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC ||
|
||||
Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC ||
|
||||
Opc == Mips::BEQZC || Opc == Mips::BNEZC ||
|
||||
Opc == Mips::BC) ? Opc : 0;
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MM32R6
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@j = global i32 10, align 4
|
||||
@ -12,9 +13,10 @@ entry:
|
||||
%cmp = icmp slt i32 %0, %1
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MM32R6: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
|
||||
@ -1,9 +1,12 @@
|
||||
; RUN: llc -march=mipsel < %s | FileCheck %s
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic < %s -asm-show-inst | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@g1 = external global i32
|
||||
|
||||
; CHECK-LABEL: seteq0:
|
||||
; CHECK: sltiu ${{[0-9]+}}, $4, 1
|
||||
; CHECK: sltiu ${{[0-9]+}}, $4, 1
|
||||
; MMR6: sltiu ${{[0-9]+}}, $4, 1
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
|
||||
|
||||
define i32 @seteq0(i32 %a) {
|
||||
entry:
|
||||
@ -13,7 +16,9 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: setne0:
|
||||
; CHECK: sltu ${{[0-9]+}}, $zero, $4
|
||||
; CHECK: sltu ${{[0-9]+}}, $zero, $4
|
||||
; MMR6: sltu ${{[0-9]+}}, $zero, $4
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
|
||||
|
||||
define i32 @setne0(i32 %a) {
|
||||
entry:
|
||||
@ -23,8 +28,10 @@ entry:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: slti_beq0:
|
||||
; CHECK: slti $[[R0:[0-9]+]], $4, -32768
|
||||
; CHECK: beqz $[[R0]]
|
||||
; CHECK: slti $[[R0:[0-9]+]], $4, -32768
|
||||
; MMR6: slti $[[R0:[0-9]+]], $4, -32768
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
|
||||
; CHECK: beqz $[[R0]]
|
||||
|
||||
define void @slti_beq0(i32 %a) {
|
||||
entry:
|
||||
@ -40,7 +47,9 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: slti_beq1:
|
||||
; CHECK: slt ${{[0-9]+}}
|
||||
; CHECK: slt ${{[0-9]+}}
|
||||
; MMR6: slt ${{[0-9]+}}
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLT_MM
|
||||
|
||||
define void @slti_beq1(i32 %a) {
|
||||
entry:
|
||||
@ -56,8 +65,10 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: slti_beq2:
|
||||
; CHECK: slti $[[R0:[0-9]+]], $4, 32767
|
||||
; CHECK: beqz $[[R0]]
|
||||
; CHECK: slti $[[R0:[0-9]+]], $4, 32767
|
||||
; MMR6: slti $[[R0:[0-9]+]], $4, 32767
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTi_MM
|
||||
; CHECK: beqz $[[R0]]
|
||||
|
||||
define void @slti_beq2(i32 %a) {
|
||||
entry:
|
||||
@ -73,7 +84,9 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: slti_beq3:
|
||||
; CHECK: slt ${{[0-9]+}}
|
||||
; CHECK: slt ${{[0-9]+}}
|
||||
; MMR6: slt ${{[0-9]+}}
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLT_MM
|
||||
|
||||
define void @slti_beq3(i32 %a) {
|
||||
entry:
|
||||
@ -89,8 +102,10 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sltiu_beq0:
|
||||
; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
|
||||
; CHECK: beqz $[[R0]]
|
||||
; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
|
||||
; MMR6: sltiu $[[R0:[0-9]+]], $4, 32767
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
|
||||
; CHECK: beqz $[[R0]]
|
||||
|
||||
define void @sltiu_beq0(i32 %a) {
|
||||
entry:
|
||||
@ -106,7 +121,9 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sltiu_beq1:
|
||||
; CHECK: sltu ${{[0-9]+}}
|
||||
; CHECK: sltu ${{[0-9]+}}
|
||||
; MMR6: sltu ${{[0-9]+}}
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
|
||||
|
||||
define void @sltiu_beq1(i32 %a) {
|
||||
entry:
|
||||
@ -122,8 +139,10 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sltiu_beq2:
|
||||
; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
|
||||
; CHECK: beqz $[[R0]]
|
||||
; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
|
||||
; MMR6: sltiu $[[R0:[0-9]+]], $4, -32768
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTiu_MM
|
||||
; CHECK: beqz $[[R0]]
|
||||
|
||||
define void @sltiu_beq2(i32 %a) {
|
||||
entry:
|
||||
@ -139,7 +158,9 @@ if.end:
|
||||
}
|
||||
|
||||
; CHECK-LABEL: sltiu_beq3:
|
||||
; CHECK: sltu ${{[0-9]+}}
|
||||
; CHECK: sltu ${{[0-9]+}}
|
||||
; MMR6: sltu ${{[0-9]+}}
|
||||
; MMR6: <MCInst #{{[0-9]+}} SLTu_MM
|
||||
|
||||
define void @sltiu_beq3(i32 %a) {
|
||||
entry:
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@i = global i32 1, align 4
|
||||
@j = global i32 10, align 4
|
||||
@ -13,9 +14,10 @@ entry:
|
||||
%cmp = icmp eq i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
|
||||
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
|
||||
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
|
||||
; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@i = global i32 0, align 4
|
||||
@j = global i32 99, align 4
|
||||
@ -11,14 +12,16 @@ entry:
|
||||
%cmp = icmp eq i32 %0, 0
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltiu ${{[0-9]+}}, 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: sltiu ${{[0-9]+}}, 1
|
||||
; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
%1 = load i32, i32* @j, align 4
|
||||
%cmp1 = icmp eq i32 %1, 99
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
store i32 %conv2, i32* @r2, align 4
|
||||
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
|
||||
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: xor $[[REGISTER:[0-9A-Ba-b_]+]], ${{[0-9]+}}
|
||||
; 16: sltiu $[[REGISTER:[0-9A-Ba-b_]+]], 1
|
||||
; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 -5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -16,9 +17,10 @@ entry:
|
||||
%cmp = icmp sge i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
%2 = load i32, i32* @m, align 4
|
||||
%cmp1 = icmp sge i32 %0, %2
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@k = global i32 10, align 4
|
||||
@r1 = common global i32 0, align 4
|
||||
@ -11,8 +12,9 @@ entry:
|
||||
%cmp = icmp sgt i32 %0, -32769
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: slti ${{[0-9]+}}, -32768
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: slti ${{[0-9]+}}, -32768
|
||||
; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: xor ${{[0-9]+}}, ${{[0-9]+}}
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 -5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -15,9 +16,10 @@ entry:
|
||||
%cmp = icmp sle i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
%2 = load i32, i32* @m, align 4
|
||||
%cmp1 = icmp sle i32 %2, %1
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 -5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -15,7 +16,8 @@ entry:
|
||||
%cmp = icmp slt i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: slt ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mattr=micromips -mcpu=mips32r6 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 -5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -14,7 +15,8 @@ entry:
|
||||
%cmp = icmp slt i32 %0, 10
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: slti $[[REGISTER:[0-9]+]], 10
|
||||
; 16: move $[[REGISTER]], $24
|
||||
; 16: slti $[[REGISTER:[0-9]+]], 10
|
||||
; MMR6: slti $[[REGISTER:[0-9]+]], $[[REGISTER:[0-9]+]], 10
|
||||
; 16: move $[[REGISTER]], $24
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@i = global i32 1, align 4
|
||||
@j = global i32 10, align 4
|
||||
@ -13,8 +14,9 @@ entry:
|
||||
%cmp = icmp ne i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
|
||||
; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: xor $[[REGISTER:[0-9]+]], ${{[0-9]+}}
|
||||
; 16: sltu ${{[0-9]+}}, $[[REGISTER]]
|
||||
; MMR6: sltu ${{[0-9]+}}, $zero, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -15,9 +16,10 @@ entry:
|
||||
%cmp = icmp uge i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
%2 = load i32, i32* @m, align 4
|
||||
%cmp1 = icmp uge i32 %0, %2
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -15,7 +16,8 @@ entry:
|
||||
%cmp = icmp ugt i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -15,9 +16,10 @@ entry:
|
||||
%cmp = icmp ule i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move $[[REGISTER:[0-9]+]], $24
|
||||
; 16: xor $[[REGISTER]], ${{[0-9]+}}
|
||||
%2 = load i32, i32* @m, align 4
|
||||
%cmp1 = icmp ule i32 %2, %1
|
||||
%conv2 = zext i1 %cmp1 to i32
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -15,7 +16,8 @@ entry:
|
||||
%cmp = icmp ult i32 %0, %1
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; MMR6: sltu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
; RUN: llc -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
; RUN: llc -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@k = global i32 10, align 4
|
||||
@ -14,7 +15,8 @@ entry:
|
||||
%cmp = icmp ult i32 %0, 10
|
||||
%conv = zext i1 %cmp to i32
|
||||
store i32 %conv, i32* @r1, align 4
|
||||
; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
; 16: sltiu ${{[0-9]+}}, 10 # 16 bit inst
|
||||
; MMR6: sltiu ${{[0-9]+}}, ${{[0-9]+}}, 1
|
||||
; 16: move ${{[0-9]+}}, $24
|
||||
ret void
|
||||
}
|
||||
|
||||
18
test/CodeGen/Mips/slt.ll
Normal file
18
test/CodeGen/Mips/slt.ll
Normal file
@ -0,0 +1,18 @@
|
||||
; RUN: llc -march=mips -mcpu=mips32r3 -mattr=micromips -relocation-model=pic < %s | FileCheck %s
|
||||
|
||||
define i32 @slt(i32 signext %a) nounwind readnone {
|
||||
%1 = icmp slt i32 %a, 7
|
||||
; CHECK-LABEL: slt:
|
||||
; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
|
||||
%2 = select i1 %1, i32 3, i32 4
|
||||
ret i32 %2
|
||||
}
|
||||
|
||||
define i32 @sgt(i32 signext %a) {
|
||||
entry:
|
||||
; CHECK-LABEL: sgt:
|
||||
%cmp = icmp sgt i32 %a, 32767
|
||||
; CHECK: slt ${{[0-9]+}}, ${{[0-9]+}}, $4
|
||||
%cond = select i1 %cmp, i32 7, i32 5
|
||||
ret i32 %cond
|
||||
}
|
||||
@ -270,6 +270,10 @@
|
||||
0x55 0x04 0x12 0x38 # CHECK: seleqz.d $f2, $f4, $f8
|
||||
0x54 0x62 0x08 0x78 # CHECK: selnez.s $f1, $f2, $f3
|
||||
0x55 0x04 0x12 0x78 # CHECK: selnez.d $f2, $f4, $f8
|
||||
0x00 0xa4 0x1b 0x50 # CHECK: slt $3, $4, $5
|
||||
0x90 0x64 0x01 0x00 # CHECK: slti $3, $4, 256
|
||||
0xb0 0x64 0x01 0x00 # CHECK: sltiu $3, $4, 256
|
||||
0x00 0xa4 0x1b 0x90 # CHECK: sltu $3, $4, $5
|
||||
0x54 0x62 0x00 0x60 # CHECK: class.s $f2, $f3
|
||||
0x54 0x82 0x02 0x60 # CHECK: class.d $f2, $f4
|
||||
0x00 0x00 0x47 0x7c # CHECK: di
|
||||
|
||||
@ -16,7 +16,7 @@ main:
|
||||
addiu $sp, $sp, -16
|
||||
bnez $9, lab1
|
||||
|
||||
# CHECK: 09 b4 04 00 bne $9, $zero, 8
|
||||
# CHECK: 09 b4 04 00 bnez $9, 8
|
||||
|
||||
addu $zero, $zero, $zero
|
||||
lab1:
|
||||
|
||||
@ -288,6 +288,10 @@
|
||||
seleqz.d $f2, $f4, $f8 # CHECK: seleqz.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x38]
|
||||
selnez.s $f1, $f2, $f3 # CHECK: selnez.s $f1, $f2, $f3 # encoding: [0x54,0x62,0x08,0x78]
|
||||
selnez.d $f2, $f4, $f8 # CHECK: selnez.d $f2, $f4, $f8 # encoding: [0x55,0x04,0x12,0x78]
|
||||
slt $3, $4, $5 # CHECK: slt $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x50]
|
||||
slti $3, $4, 256 # CHECK: slti $3, $4, 256 # encoding: [0x90,0x64,0x01,0x00]
|
||||
sltiu $3, $4, 256 # CHECK: sltiu $3, $4, 256 # encoding: [0xb0,0x64,0x01,0x00]
|
||||
sltu $3, $4, $5 # CHECK: sltu $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x90]
|
||||
class.s $f2, $f3 # CHECK: class.s $f2, $f3 # encoding: [0x54,0x62,0x00,0x60]
|
||||
class.d $f2, $f4 # CHECK: class.d $f2, $f4 # encoding: [0x54,0x82,0x02,0x60]
|
||||
deret # CHECK: deret # encoding: [0x00,0x00,0xe3,0x7c]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user