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Print symbolic SubRegIndex names on machine operands.

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llvm-svn: 104628
This commit is contained in:
Jakob Stoklund Olesen 2010-05-25 19:49:38 +00:00
parent 696fbed514
commit 9210d3b189
4 changed files with 30 additions and 4 deletions
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9
include/llvm/Target/TargetRegisterInfo.h
View File

@ -268,6 +268,7 @@ public:
typedef const TargetRegisterClass * const * regclass_iterator;
private:
const TargetRegisterDesc *Desc; // Pointer to the descriptor array
const char *const *SubRegIndexNames; // Names of subreg indexes.
unsigned NumRegs; // Number of entries in the array
regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
@ -278,6 +279,7 @@ protected:
TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RegClassBegin,
regclass_iterator RegClassEnd,
const char *const *subregindexnames,
int CallFrameSetupOpcode = -1,
int CallFrameDestroyOpcode = -1,
const unsigned* subregs = 0,
@ -378,6 +380,13 @@ public:
return NumRegs;
}
/// getSubRegIndexName - Return the human-readable symbolic target-specific
/// name for the specified SubRegIndex.
const char *getSubRegIndexName(unsigned SubIdx) const {
assert(SubIdx && "This is not a subregister index");
return SubRegIndexNames[SubIdx-1];
}
/// regsOverlap - Returns true if the two registers are equal or alias each
/// other. The registers may be virtual register.
bool regsOverlap(unsigned regA, unsigned regB) const {

8
lib/CodeGen/MachineInstr.cpp
View File

@ -219,8 +219,12 @@ void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
OS << "%physreg" << getReg();
}
if (getSubReg() != 0)
OS << ':' << getSubReg();
if (getSubReg() != 0) {
if (TM)
OS << ':' << TM->getRegisterInfo()->getSubRegIndexName(getSubReg());
else
OS << ':' << getSubReg();
}
if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
isEarlyClobber()) {

4
lib/Target/TargetRegisterInfo.cpp
View File

@ -22,6 +22,7 @@ using namespace llvm;
TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
regclass_iterator RCB, regclass_iterator RCE,
const char *const *subregindexnames,
int CFSO, int CFDO,
const unsigned* subregs, const unsigned subregsize,
const unsigned* superregs, const unsigned superregsize,
@ -29,7 +30,8 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
: SubregHash(subregs), SubregHashSize(subregsize),
SuperregHash(superregs), SuperregHashSize(superregsize),
AliasesHash(aliases), AliasesHashSize(aliasessize),
Desc(D), NumRegs(NR), RegClassBegin(RCB), RegClassEnd(RCE) {
Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
RegClassBegin(RCB), RegClassEnd(RCE) {
assert(NumRegs < FirstVirtualRegister &&
"Target has too many physical registers!");

13
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -811,6 +811,16 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << "Empty_SuperRegsSet },\n";
}
OS << " };\n"; // End of register descriptors...
// Emit SubRegIndex names, skipping 0
const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
OS << "\n const char *const SubRegIndexTable[] = { \"";
for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
OS << SubRegIndices[i]->getName();
if (i+1 != e)
OS << "\", \"";
}
OS << "\" };\n\n";
OS << "}\n\n"; // End of anonymous namespace...
std::string ClassName = Target.getName() + "GenRegisterInfo";
@ -876,7 +886,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
<< " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
<< ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
<< " SubRegIndexTable,\n"
<< " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
<< " SubregHashTable, SubregHashTableSize,\n"
<< " SuperregHashTable, SuperregHashTableSize,\n"