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Add some more load types in.

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llvm-svn: 112721
This commit is contained in:
Eric Christopher 2010-09-01 18:01:32 +00:00
parent f72b7040a2
commit 92238b2b5a
1 changed files with 22 additions and 2 deletions
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22
lib/Target/ARM/ARMFastISel.cpp
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@ -110,6 +110,7 @@ class ARMFastISel : public FastISel {
// Utility routines.
private:
bool isTypeLegal(const Type *Ty, EVT &VT);
bool isLoadTypeLegal(const Type *Ty, EVT &VT);
bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
bool ARMLoadAlloca(const Instruction *I);
bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
@ -323,6 +324,17 @@ bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
return TLI.isTypeLegal(VT);
}
bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
if (isTypeLegal(Ty, VT)) return true;
// If this is a type than can be sign or zero-extended to a basic operation
// go ahead and accept it now.
if (VT == MVT::i8 || VT == MVT::i16)
return true;
return false;
}
// Computes the Reg+Offset to get to an object.
bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
int &Offset) {
@ -403,6 +415,14 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
default:
assert(false && "Trying to emit for an unhandled type!");
return false;
case MVT::i16:
Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
VT = MVT::i32;
break;
case MVT::i8:
Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
VT = MVT::i32;
break;
case MVT::i32:
Opc = isThumb ? ARM::tLDR : ARM::LDR;
break;
@ -432,7 +452,7 @@ bool ARMFastISel::ARMSelectLoad(const Instruction *I) {
// Verify we have a legal type before going any further.
EVT VT;
if (!isTypeLegal(I->getType(), VT))
if (!isLoadTypeLegal(I->getType(), VT))
return false;
// Our register and offset with innocuous defaults.