From 923809763838242a2aa8d9ab672cd5a24a108853 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 26 Jul 2019 09:19:08 +0000 Subject: [PATCH] [AArch64] Define ETE and TRBE system registers Embedded Trace Extension and Trace Buffer Extension are optional future architecture extensions. (cf. https://developer.arm.com/architectures/cpu-architecture/a-profile/exploration-tools) Their system registers are documented here: https://developer.arm.com/docs/ddi0601/a ETE shares register names with ETM. One exception is the ETE TRCEXTINSELR0 register, which has the same encoding as the ETM TRCEXTINSELR register (but different semantics). This patch treats them as aliases: the assembler will accept both names, emitting identical encoding, and the disassembler will keep disassembling to TRCEXRINSELR. Differential Revision: https://reviews.llvm.org/D63707 llvm-svn: 367093 --- lib/Target/AArch64/AArch64.td | 15 ++++++++- lib/Target/AArch64/AArch64InstrInfo.td | 4 +++ lib/Target/AArch64/AArch64Subtarget.h | 4 +++ lib/Target/AArch64/AArch64SystemOperands.td | 23 +++++++++++++ test/MC/AArch64/ete-sysregs.s | 33 +++++++++++++++++++ test/MC/AArch64/trbe-sysreg-diag.s | 9 ++++++ test/MC/AArch64/trbe-sysreg.s | 35 ++++++++++++++++++++ test/MC/Disassembler/AArch64/ete.txt | 36 +++++++++++++++++++++ test/MC/Disassembler/AArch64/trbe.txt | 35 ++++++++++++++++++++ 9 files changed, 193 insertions(+), 1 deletion(-) create mode 100644 test/MC/AArch64/ete-sysregs.s create mode 100644 test/MC/AArch64/trbe-sysreg-diag.s create mode 100644 test/MC/AArch64/trbe-sysreg.s create mode 100644 test/MC/Disassembler/AArch64/ete.txt create mode 100644 test/MC/Disassembler/AArch64/trbe.txt diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td index a0d334ebb3f..6f78c6eae3c 100644 --- a/lib/Target/AArch64/AArch64.td +++ b/lib/Target/AArch64/AArch64.td @@ -345,6 +345,13 @@ def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen", def FeatureMTE : SubtargetFeature<"mte", "HasMTE", "true", "Enable Memory Tagging Extension" >; +def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE", + "true", "Enable Trace Buffer Extension">; + +def FeatureETE : SubtargetFeature<"ete", "HasETE", + "true", "Enable Embedded Trace Extension", + [FeatureTRBE]>; + //===----------------------------------------------------------------------===// // Architectures. // @@ -772,7 +779,13 @@ def : ProcessorModel<"generic", NoSchedModel, [ FeatureFuseAES, FeatureNEON, FeaturePerfMon, - FeaturePostRAScheduler + FeaturePostRAScheduler, +// ETE and TRBE are future architecture extensions. We temporariliy enable them +// by default for users targeting generic AArch64, until it is decided in which +// armv8.x-a architecture revision they will end up. The extensions do not +// affect code generated by the compiler and can be used only by explicitly +// mentioning the new system register names in assembly. + FeatureETE ]>; def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>; diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index c02c4646b3f..37cc6d7ea68 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -133,6 +133,10 @@ def HasBTI : Predicate<"Subtarget->hasBTI()">, AssemblerPredicate<"FeatureBranchTargetId", "bti">; def HasMTE : Predicate<"Subtarget->hasMTE()">, AssemblerPredicate<"FeatureMTE", "mte">; +def HasETE : Predicate<"Subtarget->hasETE()">, + AssemblerPredicate<"FeatureETE", "ete">; +def HasTRBE : Predicate<"Subtarget->hasTRBE()">, + AssemblerPredicate<"FeatureTRBE", "trbe">; def IsLE : Predicate<"Subtarget->isLittleEndian()">; def IsBE : Predicate<"!Subtarget->isLittleEndian()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index ff51a22240e..c04d6a3d22c 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -144,6 +144,10 @@ protected: bool HasSVE2SHA3 = false; bool HasSVE2BitPerm = false; + // Future architecture extensions. + bool HasETE = false; + bool HasTRBE = false; + // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove = false; diff --git a/lib/Target/AArch64/AArch64SystemOperands.td b/lib/Target/AArch64/AArch64SystemOperands.td index 536a6591478..8ca031e3fee 100644 --- a/lib/Target/AArch64/AArch64SystemOperands.td +++ b/lib/Target/AArch64/AArch64SystemOperands.td @@ -1460,6 +1460,29 @@ def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0110, 0b0110, 0b001>; def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; } // HasMTE +// Embedded Trace Extension R/W System registers +let Requires = [{ {AArch64::FeatureETE} }] in { +// Name Op0 Op1 CRn CRm Op2 +def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; +// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR +def : RWSysReg<"TRCEXTINSELR0", 0b10, 0b001, 0b0000, 0b1000, 0b100>; +def : RWSysReg<"TRCEXTINSELR1", 0b10, 0b001, 0b0000, 0b1001, 0b100>; +def : RWSysReg<"TRCEXTINSELR2", 0b10, 0b001, 0b0000, 0b1010, 0b100>; +def : RWSysReg<"TRCEXTINSELR3", 0b10, 0b001, 0b0000, 0b1011, 0b100>; +} // FeatureETE + +// Trace Buffer Extension System registers +let Requires = [{ {AArch64::FeatureTRBE} }] in { +// Name Op0 Op1 CRn CRm Op2 +def : RWSysReg<"TRBLIMITR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b000>; +def : RWSysReg<"TRBPTR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b001>; +def : RWSysReg<"TRBBASER_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b010>; +def : RWSysReg<"TRBSR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b011>; +def : RWSysReg<"TRBMAR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b100>; +def : RWSysReg<"TRBTRG_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b110>; +def : ROSysReg<"TRBIDR_EL1", 0b11, 0b000, 0b1001, 0b1011, 0b111>; +} // FeatureTRBE + // Cyclone specific system registers // Op0 Op1 CRn CRm Op2 let Requires = [{ {AArch64::ProcCyclone} }] in diff --git a/test/MC/AArch64/ete-sysregs.s b/test/MC/AArch64/ete-sysregs.s new file mode 100644 index 00000000000..5d5d7282fd6 --- /dev/null +++ b/test/MC/AArch64/ete-sysregs.s @@ -0,0 +1,33 @@ +// ETE System registers +// +// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s + +// Read from system register +mrs x0, TRCRSR +mrs x0, TRCEXTINSELR +mrs x0, TRCEXTINSELR0 +mrs x0, TRCEXTINSELR1 +mrs x0, TRCEXTINSELR2 +mrs x0, TRCEXTINSELR3 + +// CHECK: mrs x0, TRCRSR // encoding: [0x00,0x0a,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR // encoding: [0x80,0x08,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR1 // encoding: [0x80,0x09,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR2 // encoding: [0x80,0x0a,0x31,0xd5] +// CHECK: mrs x0, TRCEXTINSELR3 // encoding: [0x80,0x0b,0x31,0xd5] + +// Write to system register +msr TRCRSR, x0 +msr TRCEXTINSELR, x0 +msr TRCEXTINSELR0, x0 +msr TRCEXTINSELR1, x0 +msr TRCEXTINSELR2, x0 +msr TRCEXTINSELR3, x0 + +// CHECK: msr TRCRSR, x0 // encoding: [0x00,0x0a,0x11,0xd5] +// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5] +// CHECK: msr TRCEXTINSELR, x0 // encoding: [0x80,0x08,0x11,0xd5] +// CHECK: msr TRCEXTINSELR1, x0 // encoding: [0x80,0x09,0x11,0xd5] +// CHECK: msr TRCEXTINSELR2, x0 // encoding: [0x80,0x0a,0x11,0xd5] +// CHECK: msr TRCEXTINSELR3, x0 // encoding: [0x80,0x0b,0x11,0xd5] diff --git a/test/MC/AArch64/trbe-sysreg-diag.s b/test/MC/AArch64/trbe-sysreg-diag.s new file mode 100644 index 00000000000..92253067250 --- /dev/null +++ b/test/MC/AArch64/trbe-sysreg-diag.s @@ -0,0 +1,9 @@ +// TRBE RO System register +// +// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s + +// Write to system register +msr TRBIDR_EL1, x0 + +// CHECK: expected writable system register or pstate +// CHECK-NEXT: msr TRBIDR_EL1, x0 diff --git a/test/MC/AArch64/trbe-sysreg.s b/test/MC/AArch64/trbe-sysreg.s new file mode 100644 index 00000000000..f9ba076200b --- /dev/null +++ b/test/MC/AArch64/trbe-sysreg.s @@ -0,0 +1,35 @@ +// TRBE System registers +// +// RUN: llvm-mc -triple aarch64 -show-encoding < %s | FileCheck %s + +// Read from system register +mrs x0, TRBLIMITR_EL1 +mrs x0, TRBPTR_EL1 +mrs x0, TRBBASER_EL1 +mrs x0, TRBSR_EL1 +mrs x0, TRBMAR_EL1 +mrs x0, TRBTRG_EL1 +mrs x0, TRBIDR_EL1 + +// CHECK: mrs x0, TRBLIMITR_EL1 // encoding: [0x00,0x9b,0x38,0xd5] +// CHECK: mrs x0, TRBPTR_EL1 // encoding: [0x20,0x9b,0x38,0xd5] +// CHECK: mrs x0, TRBBASER_EL1 // encoding: [0x40,0x9b,0x38,0xd5] +// CHECK: mrs x0, TRBSR_EL1 // encoding: [0x60,0x9b,0x38,0xd5] +// CHECK: mrs x0, TRBMAR_EL1 // encoding: [0x80,0x9b,0x38,0xd5] +// CHECK: mrs x0, TRBTRG_EL1 // encoding: [0xc0,0x9b,0x38,0xd5] +// CHECK: mrs x0, TRBIDR_EL1 // encoding: [0xe0,0x9b,0x38,0xd5] + +// Write to system register +msr TRBLIMITR_EL1, x0 +msr TRBPTR_EL1, x0 +msr TRBBASER_EL1, x0 +msr TRBSR_EL1, x0 +msr TRBMAR_EL1, x0 +msr TRBTRG_EL1, x0 + +// CHECK: msr TRBLIMITR_EL1, x0 // encoding: [0x00,0x9b,0x18,0xd5] +// CHECK: msr TRBPTR_EL1, x0 // encoding: [0x20,0x9b,0x18,0xd5] +// CHECK: msr TRBBASER_EL1, x0 // encoding: [0x40,0x9b,0x18,0xd5] +// CHECK: msr TRBSR_EL1, x0 // encoding: [0x60,0x9b,0x18,0xd5] +// CHECK: msr TRBMAR_EL1, x0 // encoding: [0x80,0x9b,0x18,0xd5] +// CHECK: msr TRBTRG_EL1, x0 // encoding: [0xc0,0x9b,0x18,0xd5] diff --git a/test/MC/Disassembler/AArch64/ete.txt b/test/MC/Disassembler/AArch64/ete.txt new file mode 100644 index 00000000000..69c75609bfe --- /dev/null +++ b/test/MC/Disassembler/AArch64/ete.txt @@ -0,0 +1,36 @@ +# ETE System registers +# +# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s + +# Read from system register +[0x00,0x0a,0x31,0xd5] +# CHECK: mrs x0, TRCRSR + +[0x80,0x08,0x31,0xd5] +# CHECK: mrs x0, TRCEXTINSELR + +[0x80,0x09,0x31,0xd5] +# CHECK: mrs x0, TRCEXTINSELR1 + +[0x80,0x0a,0x31,0xd5] +# CHECK: mrs x0, TRCEXTINSELR2 + +[0x80,0x0b,0x31,0xd5] +# CHECK: mrs x0, TRCEXTINSELR3 + + +# Write to system register +[0x00,0x0a,0x11,0xd5] +# CHECK: msr TRCRSR, x0 + +[0x80,0x08,0x11,0xd5] +# CHECK: msr TRCEXTINSELR, x0 + +[0x80,0x09,0x11,0xd5] +# CHECK: msr TRCEXTINSELR1, x0 + +[0x80,0x0a,0x11,0xd5] +# CHECK: msr TRCEXTINSELR2, x0 + +[0x80,0x0b,0x11,0xd5] +# CHECK: msr TRCEXTINSELR3, x0 diff --git a/test/MC/Disassembler/AArch64/trbe.txt b/test/MC/Disassembler/AArch64/trbe.txt new file mode 100644 index 00000000000..936b2d3070f --- /dev/null +++ b/test/MC/Disassembler/AArch64/trbe.txt @@ -0,0 +1,35 @@ +# TRBE System registers +# +# RUN: llvm-mc -triple aarch64 -disassemble < %s | FileCheck %s + +# Read from system register +[0x00,0x9b,0x38,0xd5] +[0x20,0x9b,0x38,0xd5] +[0x40,0x9b,0x38,0xd5] +[0x60,0x9b,0x38,0xd5] +[0x80,0x9b,0x38,0xd5] +[0xc0,0x9b,0x38,0xd5] +[0xe0,0x9b,0x38,0xd5] + +# CHECK: mrs x0, TRBLIMITR_EL1 +# CHECK: mrs x0, TRBPTR_EL1 +# CHECK: mrs x0, TRBBASER_EL1 +# CHECK: mrs x0, TRBSR_EL1 +# CHECK: mrs x0, TRBMAR_EL1 +# CHECK: mrs x0, TRBTRG_EL1 +# CHECK: mrs x0, TRBIDR_EL1 + +# Write to system register +[0x00,0x9b,0x18,0xd5] +[0x20,0x9b,0x18,0xd5] +[0x40,0x9b,0x18,0xd5] +[0x60,0x9b,0x18,0xd5] +[0x80,0x9b,0x18,0xd5] +[0xc0,0x9b,0x18,0xd5] + +# CHECK: msr TRBLIMITR_EL1, x0 +# CHECK: msr TRBPTR_EL1, x0 +# CHECK: msr TRBBASER_EL1, x0 +# CHECK: msr TRBSR_EL1, x0 +# CHECK: msr TRBMAR_EL1, x0 +# CHECK: msr TRBTRG_EL1, x0