RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 12:43:36 +01:00
Code Issues Projects Releases Wiki Activity

[AMDGPU][MC] Corrected src0 for v_movrelsd_b32 and v_movrelsd_2_b32

Browse Source 
See https://bugs.llvm.org/show_bug.cgi?id=40903

Reviewers: arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D69888
This commit is contained in:
Dmitry Preobrazhensky 2019-11-08 16:38:56 +03:00
parent 23a035a9ad
commit 925e562580
3 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/AMDGPU/VOP1Instructions.td
View File

@ -274,13 +274,13 @@ def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> {
// to be a src operand. The custom inserter must add a tied implicit
// def and use of the super register since there seems to be no way to
// add an implicit def of a virtual register in tablegen.
def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> {
class VOP_MOVREL<RegisterOperand Src1RC> : VOPProfile<[untyped, i32, untyped, untyped]> {
let Src0RC32 = VOPDstOperand<VGPR_32>;
let Src0RC64 = VOPDstOperand<VGPR_32>;
let Outs = (outs);
let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0);
let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0);
let Ins32 = (ins Src0RC32:$vdst, Src1RC:$src0);
let Ins64 = (ins Src0RC64:$vdst, Src1RC:$src0);
let InsDPP = (ins DstRC:$vdst, DstRC:$old, Src0RC32:$src0,
dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
@ -306,6 +306,9 @@ def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> {
let EmitDst = 1; // force vdst emission
}
def VOP_MOVRELD : VOP_MOVREL<VSrc_b32>;
def VOP_MOVRELSD : VOP_MOVREL<VRegSrc_32>;
let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
// v_movreld_b32 is a special case because the destination output
// register is really a source. It isn't actually read (but may be
@ -315,7 +318,7 @@ let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
// so this must have an implicit def of the register added to it.
defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>;
defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_MOVRELSD>;
} // End Uses = [M0, EXEC]
defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>;
@ -430,9 +433,8 @@ let SubtargetPredicate = isGFX10Plus in {
defm V_PIPEFLUSH : VOP1Inst<"v_pipeflush", VOP_NONE>;
let Uses = [M0] in {
// FIXME-GFX10: Should V_MOVRELSD_2_B32 be VOP_NO_EXT?
defm V_MOVRELSD_2_B32 :
VOP1Inst<"v_movrelsd_2_b32", VOP_NO_EXT<VOP_I32_I32>>;
VOP1Inst<"v_movrelsd_2_b32", VOP_MOVRELSD>;
def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {
let Constraints = "$vdst = $src1, $vdst1 = $src0";

6
test/MC/AMDGPU/gfx10_asm_all.s
View File

@ -32199,6 +32199,9 @@ v_movrelsd_b32_e64 v255, v1
v_movrelsd_b32_e64 v5, v255
// GFX10: encoding: [0x05,0x00,0xc4,0xd5,0xff,0x01,0x00,0x00]
v_movrelsd_b32 v5, s1
// GFX10-ERR: error: invalid operand for instruction
v_movrelsd_2_b32 v5, v1
// GFX10: encoding: [0x01,0x91,0x0a,0x7e]
@ -32217,6 +32220,9 @@ v_movrelsd_2_b32_e64 v255, v1
v_movrelsd_2_b32_e64 v5, v255
// GFX10: encoding: [0x05,0x00,0xc8,0xd5,0xff,0x01,0x00,0x00]
v_movrelsd_2_b32 v5, s1
// GFX10-ERR: error: invalid operand for instruction
v_cvt_f16_u16_e32 v5, v1
// GFX10: encoding: [0x01,0xa1,0x0a,0x7e]

4
test/MC/AMDGPU/vop1.s
View File

@ -273,6 +273,10 @@ v_movrels_b32_e32 v1, v2
// VI: v_movrelsd_b32_e32 v1, v2 ; encoding: [0x02,0x71,0x02,0x7e]
v_movrelsd_b32_e32 v1, v2
// NOSICI: error: invalid operand for instruction
// NOVI: error: invalid operand for instruction
v_movrelsd_b32_e32 v1, s2
// NOSI: error: instruction not supported on this GPU
// NOSI: v_log_legacy_f32 v1, v2
// CI: v_log_legacy_f32_e32 v1, v2 ; encoding: [0x02,0x8b,0x02,0x7e]