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[LegalizeTypes] Add ROTL/ROTR to ScalarizeVectorResult.

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We can scalarize these just like any other binary operation.

Fixes https://bugs.llvm.org/show_bug.cgi?id=47303 caused by D77152.

Differential Revision: https://reviews.llvm.org/D86601
This commit is contained in:
Jay Foad 2020-08-26 09:41:23 +01:00
parent ef1ac54803
commit 9284abf90d
1 changed files with 2 additions and 0 deletions
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lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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@ -146,6 +146,8 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
case ISD::ROTL:
case ISD::ROTR:
R = ScalarizeVecRes_BinOp(N);
break;
case ISD::FMA: