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[X86] Remove unnecessary BTmi/BTmr scheduler overrides

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llvm-svn: 343487
This commit is contained in:
Simon Pilgrim 2018-10-01 15:01:00 +00:00
parent f37ff3fd38
commit 92a71efe9a
7 changed files with 9 additions and 56 deletions
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7
lib/Target/X86/X86SchedBroadwell.td Executable file → Normal file
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@ -978,13 +978,6 @@ def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
def: InstRW<[BWWriteResGroup62], (instrs FARJMP64)>;
def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[BWWriteResGroup63], (instregex "BT(16|32|64)mi8")>;
def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
let Latency = 6;
let NumMicroOps = 2;

18
lib/Target/X86/X86SchedHaswell.td
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@ -168,8 +168,8 @@ def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>;
defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
@ -645,13 +645,6 @@ def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;
//-- Arithmetic instructions --//
// BT.
// m,r.
def HWWriteBTmr : SchedWriteRes<[]> {
let NumMicroOps = 10;
}
def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>;
// BTR BTS BTC.
// m,r.
def HWWriteBTRSCmr : SchedWriteRes<[]> {
@ -994,13 +987,6 @@ def HWWriteResGroup14 : SchedWriteRes<[HWPort6,HWPort23]> {
def: InstRW<[HWWriteResGroup14], (instrs FARJMP64)>;
def: InstRW<[HWWriteResGroup14], (instregex "JMP(16|32|64)m")>;
def HWWriteResGroup15 : SchedWriteRes<[HWPort23,HWPort06]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup15], (instregex "BT(16|32|64)mi8")>;
def HWWriteResGroup16 : SchedWriteRes<[HWPort23,HWPort15]> {
let Latency = 6;
let NumMicroOps = 2;

11
lib/Target/X86/X86SchedSandyBridge.td
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@ -163,8 +163,8 @@ def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
@ -817,13 +817,6 @@ def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
}
def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
def SBWriteResGroup50 : SchedWriteRes<[SBPort23,SBPort05]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SBWriteResGroup50], (instregex "BT(16|32|64)mi8")>;
def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
let Latency = 6;
let NumMicroOps = 2;

7
lib/Target/X86/X86SchedSkylakeClient.td
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@ -1018,13 +1018,6 @@ def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64)>;
def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
let Latency = 6;
let NumMicroOps = 2;

7
lib/Target/X86/X86SchedSkylakeServer.td Executable file → Normal file
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@ -1177,13 +1177,6 @@ def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>;
def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>;
def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
let Latency = 6;
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
let Latency = 6;
let NumMicroOps = 2;

5
lib/Target/X86/X86ScheduleAtom.td
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@ -123,7 +123,7 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
}
defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [AtomPort0], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>;
defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
@ -628,8 +628,7 @@ def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> {
let Latency = 9;
let ResourceCycles = [9];
}
def : InstRW<[AtomWrite01_9], (instrs BT16mr, BT32mr, BT64mr,
POPA16, POPA32,
def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32,
PUSHF16, PUSHF32, PUSHF64,
SHLD64mrCL, SHRD64mrCL,
SHLD64mri8, SHRD64mri8,

4
lib/Target/X86/X86ScheduleZnver1.td
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@ -714,10 +714,6 @@ def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> {
let Latency = 6;
}
// BT.
// m,i.
def : InstRW<[WriteShiftLd], (instregex "BT(16|32|64)mi8")>;
// BTR BTS BTC.
// m,r,i.
def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> {