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[X86] Remove CustomInserter for FMA3 instructions. Looks like since we got full commuting support for FMAs after this was added, the coalescer can now get this right on its own.
Differential Revision: https://reviews.llvm.org/D22799 llvm-svn: 276987
This commit is contained in:
Craig Topper
parent
e4df16d417
commit
9332f50e72
@ -24236,164 +24236,6 @@ X86TargetLowering::EmitSjLjDispatchBlock(MachineInstr &MI,
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return BB;
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}
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// Replace 213-type (isel default) FMA3 instructions with 231-type for
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// accumulator loops. Writing back to the accumulator allows the coalescer
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// to remove extra copies in the loop.
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// FIXME: Do this on AVX512. We don't support 231 variants yet (PR23937).
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MachineBasicBlock *
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X86TargetLowering::emitFMA3Instr(MachineInstr &MI,
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MachineBasicBlock *MBB) const {
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MachineOperand &AddendOp = MI.getOperand(3);
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// Bail out early if the addend isn't a register - we can't switch these.
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if (!AddendOp.isReg())
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return MBB;
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MachineFunction &MF = *MBB->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Check whether the addend is defined by a PHI:
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assert(MRI.hasOneDef(AddendOp.getReg()) && "Multiple defs in SSA?");
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MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg());
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if (!AddendDef.isPHI())
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return MBB;
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// Look for the following pattern:
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// loop:
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// %addend = phi [%entry, 0], [%loop, %result]
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// ...
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// %result<tied1> = FMA213 %m2<tied0>, %m1, %addend
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// Replace with:
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// loop:
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// %addend = phi [%entry, 0], [%loop, %result]
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// ...
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// %result<tied1> = FMA231 %addend<tied0>, %m1, %m2
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for (unsigned i = 1, e = AddendDef.getNumOperands(); i < e; i += 2) {
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assert(AddendDef.getOperand(i).isReg());
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MachineOperand PHISrcOp = AddendDef.getOperand(i);
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MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg());
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if (&PHISrcInst == &MI) {
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// Found a matching instruction.
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unsigned NewFMAOpc = 0;
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switch (MI.getOpcode()) {
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case X86::VFMADD213PDr:
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NewFMAOpc = X86::VFMADD231PDr;
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break;
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case X86::VFMADD213PSr:
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NewFMAOpc = X86::VFMADD231PSr;
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break;
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case X86::VFMADD213SDr:
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NewFMAOpc = X86::VFMADD231SDr;
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break;
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case X86::VFMADD213SSr:
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NewFMAOpc = X86::VFMADD231SSr;
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break;
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case X86::VFMSUB213PDr:
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NewFMAOpc = X86::VFMSUB231PDr;
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break;
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case X86::VFMSUB213PSr:
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NewFMAOpc = X86::VFMSUB231PSr;
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break;
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case X86::VFMSUB213SDr:
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NewFMAOpc = X86::VFMSUB231SDr;
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break;
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case X86::VFMSUB213SSr:
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NewFMAOpc = X86::VFMSUB231SSr;
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break;
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case X86::VFNMADD213PDr:
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NewFMAOpc = X86::VFNMADD231PDr;
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break;
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case X86::VFNMADD213PSr:
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NewFMAOpc = X86::VFNMADD231PSr;
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break;
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case X86::VFNMADD213SDr:
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NewFMAOpc = X86::VFNMADD231SDr;
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break;
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case X86::VFNMADD213SSr:
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NewFMAOpc = X86::VFNMADD231SSr;
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break;
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case X86::VFNMSUB213PDr:
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NewFMAOpc = X86::VFNMSUB231PDr;
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break;
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case X86::VFNMSUB213PSr:
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NewFMAOpc = X86::VFNMSUB231PSr;
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break;
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case X86::VFNMSUB213SDr:
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NewFMAOpc = X86::VFNMSUB231SDr;
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break;
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case X86::VFNMSUB213SSr:
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NewFMAOpc = X86::VFNMSUB231SSr;
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break;
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case X86::VFMADDSUB213PDr:
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NewFMAOpc = X86::VFMADDSUB231PDr;
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break;
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case X86::VFMADDSUB213PSr:
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NewFMAOpc = X86::VFMADDSUB231PSr;
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break;
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case X86::VFMSUBADD213PDr:
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NewFMAOpc = X86::VFMSUBADD231PDr;
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break;
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case X86::VFMSUBADD213PSr:
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NewFMAOpc = X86::VFMSUBADD231PSr;
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break;
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case X86::VFMADD213PDYr:
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NewFMAOpc = X86::VFMADD231PDYr;
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break;
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case X86::VFMADD213PSYr:
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NewFMAOpc = X86::VFMADD231PSYr;
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break;
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case X86::VFMSUB213PDYr:
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NewFMAOpc = X86::VFMSUB231PDYr;
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break;
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case X86::VFMSUB213PSYr:
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NewFMAOpc = X86::VFMSUB231PSYr;
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break;
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case X86::VFNMADD213PDYr:
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NewFMAOpc = X86::VFNMADD231PDYr;
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break;
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case X86::VFNMADD213PSYr:
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NewFMAOpc = X86::VFNMADD231PSYr;
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break;
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case X86::VFNMSUB213PDYr:
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NewFMAOpc = X86::VFNMSUB231PDYr;
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break;
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case X86::VFNMSUB213PSYr:
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NewFMAOpc = X86::VFNMSUB231PSYr;
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break;
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case X86::VFMADDSUB213PDYr:
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NewFMAOpc = X86::VFMADDSUB231PDYr;
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break;
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case X86::VFMADDSUB213PSYr:
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NewFMAOpc = X86::VFMADDSUB231PSYr;
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break;
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case X86::VFMSUBADD213PDYr:
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NewFMAOpc = X86::VFMSUBADD231PDYr;
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break;
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case X86::VFMSUBADD213PSYr:
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NewFMAOpc = X86::VFMSUBADD231PSYr;
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break;
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default:
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llvm_unreachable("Unrecognized FMA variant.");
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}
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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MachineInstrBuilder MIB =
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BuildMI(MF, MI.getDebugLoc(), TII.get(NewFMAOpc))
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.addOperand(MI.getOperand(0))
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.addOperand(MI.getOperand(3))
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.addOperand(MI.getOperand(2))
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.addOperand(MI.getOperand(1));
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MBB->insert(MachineBasicBlock::iterator(MI), MIB);
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MI.eraseFromParent();
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}
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}
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return MBB;
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}
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MachineBasicBlock *
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X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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@ -24616,39 +24458,6 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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case TargetOpcode::PATCHPOINT:
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return emitPatchPoint(MI, BB);
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case X86::VFMADD213PDr:
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case X86::VFMADD213PSr:
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case X86::VFMADD213SDr:
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case X86::VFMADD213SSr:
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case X86::VFMSUB213PDr:
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case X86::VFMSUB213PSr:
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case X86::VFMSUB213SDr:
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case X86::VFMSUB213SSr:
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case X86::VFNMADD213PDr:
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case X86::VFNMADD213PSr:
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case X86::VFNMADD213SDr:
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case X86::VFNMADD213SSr:
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case X86::VFNMSUB213PDr:
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case X86::VFNMSUB213PSr:
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case X86::VFNMSUB213SDr:
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case X86::VFNMSUB213SSr:
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case X86::VFMADDSUB213PDr:
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case X86::VFMADDSUB213PSr:
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case X86::VFMSUBADD213PDr:
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case X86::VFMSUBADD213PSr:
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case X86::VFMADD213PDYr:
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case X86::VFMADD213PSYr:
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case X86::VFMSUB213PDYr:
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case X86::VFMSUB213PSYr:
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case X86::VFNMADD213PDYr:
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case X86::VFNMADD213PSYr:
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case X86::VFNMSUB213PDYr:
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case X86::VFNMSUB213PSYr:
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case X86::VFMADDSUB213PDYr:
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case X86::VFMADDSUB213PSYr:
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case X86::VFMSUBADD213PDYr:
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case X86::VFMSUBADD213PSYr:
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return emitFMA3Instr(MI, BB);
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case X86::LCMPXCHG8B_SAVE_EBX:
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case X86::LCMPXCHG16B_SAVE_RBX: {
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unsigned BasePtr =
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@ -39,7 +39,6 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
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PatFrag MemFrag128, PatFrag MemFrag256,
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ValueType OpVT128, ValueType OpVT256,
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SDPatternOperator Op = null_frag> {
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let usesCustomInserter = 1 in
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def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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@ -55,7 +54,6 @@ multiclass fma3p_rm<bits<8> opc, string OpcodeStr,
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[(set VR128:$dst, (OpVT128 (Op VR128:$src2, VR128:$src1,
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(MemFrag128 addr:$src3))))]>;
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let usesCustomInserter = 1 in
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def Yr : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
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(ins VR256:$src1, VR256:$src2, VR256:$src3),
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!strconcat(OpcodeStr,
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@ -144,7 +142,6 @@ let Constraints = "$src1 = $dst", isCommutable = 1, hasSideEffects = 0 in
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multiclass fma3s_rm<bits<8> opc, string OpcodeStr,
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X86MemOperand x86memop, RegisterClass RC,
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SDPatternOperator OpNode = null_frag> {
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let usesCustomInserter = 1 in
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def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src1, RC:$src2, RC:$src3),
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!strconcat(OpcodeStr,
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@ -9,9 +9,9 @@ target triple = "x86_64-apple-macosx"
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; CHECK-NOT: {{.*}}, %xmm0
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; %addr lives in rdi.
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; %addr2 lives in rsi.
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; CHECK: vmovss (%rsi), [[ADDR2:%xmm[0-9]+]]
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; CHECK: vmovss (%rdi), [[ADDR:%xmm[0-9]+]]
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; The assembly syntax is in the reverse order.
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; CHECK: vfmadd231ss (%rdi), [[ADDR2]], %xmm0
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; CHECK: vfmadd231ss (%rsi), [[ADDR]], %xmm0
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define void @test1(float* %addr, float* %addr2, float %arg) {
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entry:
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br label %loop
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