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AVX512BW: Enable AND/OR/XOR vector byte/word paked operation by promoting to qword that natively suppored.
llvm-svn: 256157
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@ -1689,6 +1689,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VSELECT, VT, Legal);
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setOperationAction(ISD::AND, VT, Promote);
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AddPromotedToType (ISD::AND, VT, MVT::v8i64);
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setOperationAction(ISD::OR, VT, Promote);
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AddPromotedToType (ISD::OR, VT, MVT::v8i64);
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setOperationAction(ISD::XOR, VT, Promote);
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AddPromotedToType (ISD::XOR, VT, MVT::v8i64);
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}
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}
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@ -13284,7 +13291,7 @@ SDValue X86TargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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&& InVT.getScalarSizeInBits() >= 32 &&
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Subtarget->hasDQI() && Subtarget->hasVLX())
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return Op; // legal, will go to VPMOVB2M, VPMOVQ2M
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}
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}
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if (VT.getVectorElementType() == MVT::i1) {
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assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");
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@ -1,9 +1,14 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s --check-prefix=ALL --check-prefix=KNL
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=skx | FileCheck %s --check-prefix=ALL --check-prefix=SKX
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; CHECK-LABEL: vpandd
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; CHECK: vpandd %zmm
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; CHECK: ret
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define <16 x i32> @vpandd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
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; ALL-LABEL: vpandd:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; ALL-NEXT: vpandd %zmm1, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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; Force the execution domain with an add.
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%a2 = add <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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@ -12,10 +17,12 @@ entry:
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpord
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; CHECK: vpord %zmm
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; CHECK: ret
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define <16 x i32> @vpord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
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; ALL-LABEL: vpord:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; ALL-NEXT: vpord %zmm1, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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; Force the execution domain with an add.
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%a2 = add <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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@ -24,10 +31,12 @@ entry:
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpxord
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; CHECK: vpxord %zmm
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; CHECK: ret
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define <16 x i32> @vpxord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ssp {
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; ALL-LABEL: vpxord:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0
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; ALL-NEXT: vpxord %zmm1, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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; Force the execution domain with an add.
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%a2 = add <16 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1,
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@ -36,10 +45,12 @@ entry:
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpandq
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; CHECK: vpandq %zmm
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; CHECK: ret
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define <8 x i64> @vpandq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
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; ALL-LABEL: vpandq:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; ALL-NEXT: vpandq %zmm1, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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@ -47,10 +58,12 @@ entry:
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ret <8 x i64> %x
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}
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; CHECK-LABEL: vporq
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; CHECK: vporq %zmm
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; CHECK: ret
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define <8 x i64> @vporq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
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; ALL-LABEL: vporq:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; ALL-NEXT: vporq %zmm1, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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@ -58,10 +71,12 @@ entry:
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ret <8 x i64> %x
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}
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; CHECK-LABEL: vpxorq
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; CHECK: vpxorq %zmm
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; CHECK: ret
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define <8 x i64> @vpxorq(<8 x i64> %a, <8 x i64> %b) nounwind uwtable readnone ssp {
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; ALL-LABEL: vpxorq:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpaddq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; ALL-NEXT: vpxorq %zmm1, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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; Force the execution domain with an add.
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%a2 = add <8 x i64> %a, <i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1, i64 1>
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@ -70,28 +85,31 @@ entry:
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}
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; CHECK-LABEL: orq_broadcast
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; CHECK: vporq LCP{{.*}}(%rip){1to8}, %zmm0, %zmm0
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; CHECK: ret
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define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
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; ALL-LABEL: orq_broadcast:
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; ALL: ## BB#0:
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; ALL-NEXT: vporq {{.*}}(%rip){1to8}, %zmm0, %zmm0
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; ALL-NEXT: retq
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%b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
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ret <8 x i64> %b
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}
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; CHECK-LABEL: andd512fold
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; CHECK: vpandd (%
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; CHECK: ret
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define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) {
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; ALL-LABEL: andd512fold:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpandd (%rdi), %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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%a = load <16 x i32>, <16 x i32>* %x, align 4
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%b = and <16 x i32> %y, %a
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ret <16 x i32> %b
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}
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; CHECK-LABEL: andqbrst
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; CHECK: vpandq (%rdi){1to8}, %zmm
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; CHECK: ret
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define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
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; ALL-LABEL: andqbrst:
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; ALL: ## BB#0: ## %entry
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; ALL-NEXT: vpandq (%rdi){1to8}, %zmm0, %zmm0
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; ALL-NEXT: retq
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entry:
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%a = load i64, i64* %ap, align 8
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%b = insertelement <8 x i64> undef, i64 %a, i32 0
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@ -99,3 +117,93 @@ entry:
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%d = and <8 x i64> %p1, %c
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ret <8 x i64>%d
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}
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define <64 x i8> @and_v64i8(<64 x i8> %a, <64 x i8> %b) {
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; KNL-LABEL: and_v64i8:
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; KNL: ## BB#0:
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; KNL-NEXT: vandps %ymm2, %ymm0, %ymm0
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; KNL-NEXT: vandps %ymm3, %ymm1, %ymm1
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; KNL-NEXT: retq
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;
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; SKX-LABEL: and_v64i8:
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; SKX: ## BB#0:
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; SKX-NEXT: vpandq %zmm1, %zmm0, %zmm0
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; SKX-NEXT: retq
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%res = and <64 x i8> %a, %b
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ret <64 x i8> %res
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}
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define <64 x i8> @or_v64i8(<64 x i8> %a, <64 x i8> %b) {
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; KNL-LABEL: or_v64i8:
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; KNL: ## BB#0:
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; KNL-NEXT: vorps %ymm2, %ymm0, %ymm0
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; KNL-NEXT: vorps %ymm3, %ymm1, %ymm1
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; KNL-NEXT: retq
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;
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; SKX-LABEL: or_v64i8:
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; SKX: ## BB#0:
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; SKX-NEXT: vporq %zmm1, %zmm0, %zmm0
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; SKX-NEXT: retq
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%res = or <64 x i8> %a, %b
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ret <64 x i8> %res
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}
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define <64 x i8> @xor_v64i8(<64 x i8> %a, <64 x i8> %b) {
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; KNL-LABEL: xor_v64i8:
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; KNL: ## BB#0:
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; KNL-NEXT: vxorps %ymm2, %ymm0, %ymm0
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; KNL-NEXT: vxorps %ymm3, %ymm1, %ymm1
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; KNL-NEXT: retq
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;
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; SKX-LABEL: xor_v64i8:
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; SKX: ## BB#0:
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; SKX-NEXT: vpxorq %zmm1, %zmm0, %zmm0
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; SKX-NEXT: retq
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%res = xor <64 x i8> %a, %b
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ret <64 x i8> %res
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}
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define <32 x i16> @and_v32i16(<32 x i16> %a, <32 x i16> %b) {
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; KNL-LABEL: and_v32i16:
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; KNL: ## BB#0:
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; KNL-NEXT: vandps %ymm2, %ymm0, %ymm0
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; KNL-NEXT: vandps %ymm3, %ymm1, %ymm1
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; KNL-NEXT: retq
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;
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; SKX-LABEL: and_v32i16:
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; SKX: ## BB#0:
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; SKX-NEXT: vpandq %zmm1, %zmm0, %zmm0
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; SKX-NEXT: retq
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%res = and <32 x i16> %a, %b
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ret <32 x i16> %res
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}
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define <32 x i16> @or_v32i16(<32 x i16> %a, <32 x i16> %b) {
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; KNL-LABEL: or_v32i16:
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; KNL: ## BB#0:
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; KNL-NEXT: vorps %ymm2, %ymm0, %ymm0
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; KNL-NEXT: vorps %ymm3, %ymm1, %ymm1
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; KNL-NEXT: retq
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;
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; SKX-LABEL: or_v32i16:
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; SKX: ## BB#0:
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; SKX-NEXT: vporq %zmm1, %zmm0, %zmm0
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; SKX-NEXT: retq
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%res = or <32 x i16> %a, %b
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ret <32 x i16> %res
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}
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define <32 x i16> @xor_v32i16(<32 x i16> %a, <32 x i16> %b) {
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; KNL-LABEL: xor_v32i16:
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; KNL: ## BB#0:
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; KNL-NEXT: vxorps %ymm2, %ymm0, %ymm0
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; KNL-NEXT: vxorps %ymm3, %ymm1, %ymm1
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; KNL-NEXT: retq
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;
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; SKX-LABEL: xor_v32i16:
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; SKX: ## BB#0:
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; SKX-NEXT: vpxorq %zmm1, %zmm0, %zmm0
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; SKX-NEXT: retq
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%res = xor <32 x i16> %a, %b
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ret <32 x i16> %res
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}
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