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[ARMv8] Add NEON instructions VCVT{A, N, P, M}.
llvm-svn: 186574
This commit is contained in:
Joey Gouly
parent
be2932828b
commit
933fb028d7
@ -127,6 +127,8 @@ class Neon_CvtFxToFP_Intrinsic
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: Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_CvtFPToFx_Intrinsic
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: Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
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class Neon_CvtFPtoInt_1Arg_Intrinsic
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: Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
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// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
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// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
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@ -319,6 +321,16 @@ def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
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// Vector Reciprocal Square Root Estimate.
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def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
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// Vector Conversions Between Floating-point and Integer
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def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
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def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
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// Vector Conversions Between Floating-point and Fixed-point.
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def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
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def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
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@ -1964,6 +1964,35 @@ class N2V<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
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let Inst{5} = Vm{4};
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}
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// Same as N2V but not predicated.
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class N2Vnp<bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
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dag oops, dag iops, InstrItinClass itin, string OpcodeStr,
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string Dt, ValueType ResTy, ValueType OpTy, list<dag> pattern>
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: NeonInp<oops, iops, AddrModeNone, IndexModeNone, N2RegFrm, itin,
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OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
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bits<5> Vd;
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bits<5> Vm;
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// Encode instruction operands
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let Inst{22} = Vd{4};
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let Inst{15-12} = Vd{3-0};
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let Inst{5} = Vm{4};
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let Inst{3-0} = Vm{3-0};
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// Encode constant bits
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let Inst{27-23} = 0b00111;
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let Inst{21-20} = 0b11;
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let Inst{19-18} = 0b10;
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let Inst{17-16} = op17_16;
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let Inst{11} = 0;
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let Inst{10-8} = op10_8;
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let Inst{7} = op7;
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let Inst{6} = op6;
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let Inst{4} = 0;
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let DecoderNamespace = "NEON";
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}
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// Same as N2V except it doesn't have a datatype suffix.
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class N2VX<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, bits<2> op17_16,
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bits<5> op11_7, bit op6, bit op4,
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@ -2379,6 +2379,21 @@ class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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(ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
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// Same as above, but not predicated.
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class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
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: N2Vnp<op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
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itin, OpcodeStr, Dt, ResTy, OpTy,
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
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class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
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InstrItinClass itin, string OpcodeStr, string Dt,
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ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
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: N2Vnp<op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
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itin, OpcodeStr, Dt, ResTy, OpTy,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
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// Narrow 2-register operations.
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class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
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bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
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@ -5431,6 +5446,26 @@ def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
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def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
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v4f32, v4i32, uint_to_fp>;
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// VCVT{A, N, P, M}
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multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
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SDPatternOperator IntU> {
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let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
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def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
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"s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
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def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
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"s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
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def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
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"u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
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def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
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"u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
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}
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}
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defm VCVTAn : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
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defm VCVTNn : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
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defm VCVTPn : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
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defm VCVTMn : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
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// VCVT : Vector Convert Between Floating-Point and Fixed-Point.
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let DecoderMethod = "DecodeVCVTD" in {
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def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
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@ -8,3 +8,39 @@ vminnm.f32 d5, d4, d30
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@ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x3e,0x5f,0x24,0xf3]
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vminnm.f32 q0, q13, q2
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@ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0xd4,0x0f,0x2a,0xf3]
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vcvta.s32.f32 d4, d6
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@ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3]
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vcvta.u32.f32 d12, d10
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@ CHECK: vcvta.u32.f32 d12, d10 @ encoding: [0x8a,0xc0,0xbb,0xf3]
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vcvta.s32.f32 q4, q6
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@ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0x4c,0x80,0xbb,0xf3]
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vcvta.u32.f32 q4, q10
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@ CHECK: vcvta.u32.f32 q4, q10 @ encoding: [0xe4,0x80,0xbb,0xf3]
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vcvtm.s32.f32 d1, d30
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@ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0x2e,0x13,0xbb,0xf3]
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vcvtm.u32.f32 d12, d10
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@ CHECK: vcvtm.u32.f32 d12, d10 @ encoding: [0x8a,0xc3,0xbb,0xf3]
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vcvtm.s32.f32 q1, q10
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@ CHECK: vcvtm.s32.f32 q1, q10 @ encoding: [0x64,0x23,0xbb,0xf3]
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vcvtm.u32.f32 q13, q1
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@ CHECK: vcvtm.u32.f32 q13, q1 @ encoding: [0xc2,0xa3,0xfb,0xf3]
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vcvtn.s32.f32 d15, d17
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@ CHECK: vcvtn.s32.f32 d15, d17 @ encoding: [0x21,0xf1,0xbb,0xf3]
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vcvtn.u32.f32 d5, d3
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@ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0x83,0x51,0xbb,0xf3]
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vcvtn.s32.f32 q3, q8
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@ CHECK: vcvtn.s32.f32 q3, q8 @ encoding: [0x60,0x61,0xbb,0xf3]
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vcvtn.u32.f32 q5, q3
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@ CHECK: vcvtn.u32.f32 q5, q3 @ encoding: [0xc6,0xa1,0xbb,0xf3]
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vcvtp.s32.f32 d11, d21
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@ CHECK: vcvtp.s32.f32 d11, d21 @ encoding: [0x25,0xb2,0xbb,0xf3]
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vcvtp.u32.f32 d14, d23
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@ CHECK: vcvtp.u32.f32 d14, d23 @ encoding: [0xa7,0xe2,0xbb,0xf3]
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vcvtp.s32.f32 q4, q15
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@ CHECK: vcvtp.s32.f32 q4, q15 @ encoding: [0x6e,0x82,0xbb,0xf3]
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vcvtp.u32.f32 q9, q8
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@ CHECK: vcvtp.u32.f32 q9, q8 @ encoding: [0xe0,0x22,0xfb,0xf3]
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@ -8,3 +8,39 @@ vminnm.f32 d5, d4, d30
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@ CHECK: vminnm.f32 d5, d4, d30 @ encoding: [0x24,0xff,0x3e,0x5f]
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vminnm.f32 q0, q13, q2
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@ CHECK: vminnm.f32 q0, q13, q2 @ encoding: [0x2a,0xff,0xd4,0x0f]
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vcvta.s32.f32 d4, d6
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@ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0xbb,0xff,0x06,0x40]
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vcvta.u32.f32 d12, d10
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@ CHECK: vcvta.u32.f32 d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc0]
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vcvta.s32.f32 q4, q6
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@ CHECK: vcvta.s32.f32 q4, q6 @ encoding: [0xbb,0xff,0x4c,0x80]
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vcvta.u32.f32 q4, q10
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@ CHECK: vcvta.u32.f32 q4, q10 @ encoding: [0xbb,0xff,0xe4,0x80]
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vcvtm.s32.f32 d1, d30
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@ CHECK: vcvtm.s32.f32 d1, d30 @ encoding: [0xbb,0xff,0x2e,0x13]
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vcvtm.u32.f32 d12, d10
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@ CHECK: vcvtm.u32.f32 d12, d10 @ encoding: [0xbb,0xff,0x8a,0xc3]
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vcvtm.s32.f32 q1, q10
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@ CHECK: vcvtm.s32.f32 q1, q10 @ encoding: [0xbb,0xff,0x64,0x23]
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vcvtm.u32.f32 q13, q1
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@ CHECK: vcvtm.u32.f32 q13, q1 @ encoding: [0xfb,0xff,0xc2,0xa3]
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vcvtn.s32.f32 d15, d17
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@ CHECK: vcvtn.s32.f32 d15, d17 @ encoding: [0xbb,0xff,0x21,0xf1]
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vcvtn.u32.f32 d5, d3
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@ CHECK: vcvtn.u32.f32 d5, d3 @ encoding: [0xbb,0xff,0x83,0x51]
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vcvtn.s32.f32 q3, q8
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@ CHECK: vcvtn.s32.f32 q3, q8 @ encoding: [0xbb,0xff,0x60,0x61]
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vcvtn.u32.f32 q5, q3
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@ CHECK: vcvtn.u32.f32 q5, q3 @ encoding: [0xbb,0xff,0xc6,0xa1]
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vcvtp.s32.f32 d11, d21
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@ CHECK: vcvtp.s32.f32 d11, d21 @ encoding: [0xbb,0xff,0x25,0xb2]
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vcvtp.u32.f32 d14, d23
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@ CHECK: vcvtp.u32.f32 d14, d23 @ encoding: [0xbb,0xff,0xa7,0xe2]
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vcvtp.s32.f32 q4, q15
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@ CHECK: vcvtp.s32.f32 q4, q15 @ encoding: [0xbb,0xff,0x6e,0x82]
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vcvtp.u32.f32 q9, q8
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@ CHECK: vcvtp.u32.f32 q9, q8 @ encoding: [0xfb,0xff,0xe0,0x22]
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@ -8,3 +8,39 @@
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# CHECK: vminnm.f32 d5, d4, d30
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0xd4 0x0f 0x2a 0xf3
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# CHECK: vminnm.f32 q0, q13, q2
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0x06 0x40 0xbb 0xf3
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# CHECK: vcvta.s32.f32 d4, d6
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0x8a 0xc0 0xbb 0xf3
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# CHECK: vcvta.u32.f32 d12, d10
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0x4c 0x80 0xbb 0xf3
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# CHECK: vcvta.s32.f32 q4, q6
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0xe4 0x80 0xbb 0xf3
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# CHECK: vcvta.u32.f32 q4, q10
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0x2e 0x13 0xbb 0xf3
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# CHECK: vcvtm.s32.f32 d1, d30
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0x8a 0xc3 0xbb 0xf3
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# CHECK: vcvtm.u32.f32 d12, d10
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0x64 0x23 0xbb 0xf3
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# CHECK: vcvtm.s32.f32 q1, q10
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0xc2 0xa3 0xfb 0xf3
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# CHECK: vcvtm.u32.f32 q13, q1
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0x21 0xf1 0xbb 0xf3
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# CHECK: vcvtn.s32.f32 d15, d17
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0x83 0x51 0xbb 0xf3
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# CHECK: vcvtn.u32.f32 d5, d3
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0x60 0x61 0xbb 0xf3
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# CHECK: vcvtn.s32.f32 q3, q8
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0xc6 0xa1 0xbb 0xf3
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# CHECK: vcvtn.u32.f32 q5, q3
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0x25 0xb2 0xbb 0xf3
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# CHECK: vcvtp.s32.f32 d11, d21
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0xa7 0xe2 0xbb 0xf3
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# CHECK: vcvtp.u32.f32 d14, d23
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0x6e 0x82 0xbb 0xf3
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# CHECK: vcvtp.s32.f32 q4, q15
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0xe0 0x22 0xfb 0xf3
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# CHECK: vcvtp.u32.f32 q9, q8
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@ -8,3 +8,39 @@
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# CHECK: vminnm.f32 d5, d4, d30
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0x2a 0xff 0xd4 0x0f
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# CHECK: vminnm.f32 q0, q13, q2
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0xbb 0xff 0x06 0x40
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# CHECK: vcvta.s32.f32 d4, d6
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0xbb 0xff 0x8a 0xc0
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# CHECK: vcvta.u32.f32 d12, d10
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0xbb 0xff 0x4c 0x80
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# CHECK: vcvta.s32.f32 q4, q6
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0xbb 0xff 0xe4 0x80
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# CHECK: vcvta.u32.f32 q4, q10
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0xbb 0xff 0x2e 0x13
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# CHECK: vcvtm.s32.f32 d1, d30
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0xbb 0xff 0x8a 0xc3
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# CHECK: vcvtm.u32.f32 d12, d10
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0xbb 0xff 0x64 0x23
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# CHECK: vcvtm.s32.f32 q1, q10
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0xfb 0xff 0xc2 0xa3
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# CHECK: vcvtm.u32.f32 q13, q1
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0xbb 0xff 0x21 0xf1
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# CHECK: vcvtn.s32.f32 d15, d17
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0xbb 0xff 0x83 0x51
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# CHECK: vcvtn.u32.f32 d5, d3
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0xbb 0xff 0x60 0x61
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# CHECK: vcvtn.s32.f32 q3, q8
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0xbb 0xff 0xc6 0xa1
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# CHECK: vcvtn.u32.f32 q5, q3
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0xbb 0xff 0x25 0xb2
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# CHECK: vcvtp.s32.f32 d11, d21
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0xbb 0xff 0xa7 0xe2
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# CHECK: vcvtp.u32.f32 d14, d23
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0xbb 0xff 0x6e 0x82
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# CHECK: vcvtp.s32.f32 q4, q15
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0xfb 0xff 0xe0 0x22
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# CHECK: vcvtp.u32.f32 q9, q8
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