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AMDGPU: Eliminate BUFFER_ATOMIC_PK_ADD_F16 node

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This is redundant with the other no return buffer atomic node, and we
don't really need a separate type profile for it.
This commit is contained in:
Matt Arsenault 2020-08-04 21:20:39 -04:00
parent 1a65e8de72
commit 933fc1e514
5 changed files with 6 additions and 11 deletions
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1
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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@ -4371,7 +4371,6 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP) NODE_NAME_CASE(BUFFER_ATOMIC_CMPSWAP)
NODE_NAME_CASE(BUFFER_ATOMIC_CSUB) NODE_NAME_CASE(BUFFER_ATOMIC_CSUB)
NODE_NAME_CASE(BUFFER_ATOMIC_FADD) NODE_NAME_CASE(BUFFER_ATOMIC_FADD)
NODE_NAME_CASE(BUFFER_ATOMIC_PK_FADD)
NODE_NAME_CASE(ATOMIC_PK_FADD) NODE_NAME_CASE(ATOMIC_PK_FADD)
case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break; case AMDGPUISD::LAST_AMDGPU_ISD_NUMBER: break;

1
lib/Target/AMDGPU/AMDGPUISelLowering.h
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@ -536,7 +536,6 @@ enum NodeType : unsigned {
BUFFER_ATOMIC_CMPSWAP, BUFFER_ATOMIC_CMPSWAP,
BUFFER_ATOMIC_CSUB, BUFFER_ATOMIC_CSUB,
BUFFER_ATOMIC_FADD, BUFFER_ATOMIC_FADD,
BUFFER_ATOMIC_PK_FADD,
ATOMIC_PK_FADD, ATOMIC_PK_FADD,
LAST_AMDGPU_ISD_NUMBER LAST_AMDGPU_ISD_NUMBER

2
lib/Target/AMDGPU/BUFInstructions.td
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@ -1432,7 +1432,7 @@ multiclass BufferAtomicPatterns_NO_RTN<SDPatternOperator name, ValueType vt,
let SubtargetPredicate = HasAtomicFaddInsts in { let SubtargetPredicate = HasAtomicFaddInsts in {
defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_fadd, f32, "BUFFER_ATOMIC_ADD_F32">; defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_fadd, f32, "BUFFER_ATOMIC_ADD_F32">;
defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_pk_fadd, v2f16, "BUFFER_ATOMIC_PK_ADD_F16">; defm : BufferAtomicPatterns_NO_RTN<SIbuffer_atomic_fadd, v2f16, "BUFFER_ATOMIC_PK_ADD_F16">;
} }
def : GCNPat< def : GCNPat<

5
lib/Target/AMDGPU/SIISelLowering.cpp
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@ -7531,10 +7531,9 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
auto *M = cast<MemSDNode>(Op); auto *M = cast<MemSDNode>(Op);
M->getMemOperand()->setOffset(Offset); M->getMemOperand()->setOffset(Offset);
unsigned Opcode = VT.isVector() ? AMDGPUISD::BUFFER_ATOMIC_PK_FADD
: AMDGPUISD::BUFFER_ATOMIC_FADD;
return DAG.getMemIntrinsicNode(Opcode, DL, Op->getVTList(), Ops, VT, return DAG.getMemIntrinsicNode(AMDGPUISD::BUFFER_ATOMIC_FADD, DL,
Op->getVTList(), Ops, VT,
M->getMemOperand()); M->getMemOperand());
} }

8
lib/Target/AMDGPU/SIInstrInfo.td
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@ -173,10 +173,9 @@ class SDBufferAtomic<string opcode> : SDNode <opcode,
[SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore] [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
>; >;
class SDBufferAtomicNoRtn<string opcode, ValueType ty> : SDNode <opcode, class SDBufferAtomicNoRtn<string opcode> : SDNode <opcode,
SDTypeProfile<0, 8, SDTypeProfile<0, 8,
[SDTCisVT<0, ty>, // vdata [SDTCisVT<1, v4i32>, // rsrc
SDTCisVT<1, v4i32>, // rsrc
SDTCisVT<2, i32>, // vindex(VGPR) SDTCisVT<2, i32>, // vindex(VGPR)
SDTCisVT<3, i32>, // voffset(VGPR) SDTCisVT<3, i32>, // voffset(VGPR)
SDTCisVT<4, i32>, // soffset(SGPR) SDTCisVT<4, i32>, // soffset(SGPR)
@ -199,8 +198,7 @@ def SIbuffer_atomic_xor : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_XOR">;
def SIbuffer_atomic_inc : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_INC">; def SIbuffer_atomic_inc : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_INC">;
def SIbuffer_atomic_dec : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_DEC">; def SIbuffer_atomic_dec : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_DEC">;
def SIbuffer_atomic_csub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_CSUB">; def SIbuffer_atomic_csub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_CSUB">;
def SIbuffer_atomic_fadd : SDBufferAtomicNoRtn <"AMDGPUISD::BUFFER_ATOMIC_FADD", f32>; def SIbuffer_atomic_fadd : SDBufferAtomicNoRtn <"AMDGPUISD::BUFFER_ATOMIC_FADD">;
def SIbuffer_atomic_pk_fadd : SDBufferAtomicNoRtn <"AMDGPUISD::BUFFER_ATOMIC_PK_FADD", v2f16>;
def SIbuffer_atomic_cmpswap : SDNode <"AMDGPUISD::BUFFER_ATOMIC_CMPSWAP", def SIbuffer_atomic_cmpswap : SDNode <"AMDGPUISD::BUFFER_ATOMIC_CMPSWAP",
SDTypeProfile<1, 9, SDTypeProfile<1, 9,