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- Handle special scalar_to_vector case: splats. Using a native 128-bit
shuffle before inserting on a 256-bit vector. - Add AVX versions of movd/movq instructions - Introduce a few COPY patterns to match insert_subvector instructions. This turns a trivial insert_subvector instruction into a register copy, coalescing the xmm into a ymm and avoid emiting on more instruction. llvm-svn: 136002
This commit is contained in:
Bruno Cardoso Lopes
parent
c13bd4fd8c
commit
9380919dc5
@ -3955,6 +3955,34 @@ static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) {
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return DAG.getNode(ISD::BITCAST, dl, VT, V);
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}
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/// PromoteVectorToScalarSplat - Since there's no native support for
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/// scalar_to_vector for 256-bit AVX, a 128-bit scalar_to_vector +
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/// INSERT_SUBVECTOR is generated. Recognize this idiom and do the
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/// shuffle before the insertion, this yields less instructions in the end.
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static SDValue PromoteVectorToScalarSplat(ShuffleVectorSDNode *SV,
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SelectionDAG &DAG) {
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EVT SrcVT = SV->getValueType(0);
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SDValue V1 = SV->getOperand(0);
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DebugLoc dl = SV->getDebugLoc();
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int NumElems = SrcVT.getVectorNumElements();
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assert(SrcVT.is256BitVector() && "unknown howto handle vector type");
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SmallVector<int, 4> Mask;
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for (int i = 0; i < NumElems/2; ++i)
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Mask.push_back(SV->getMaskElt(i));
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EVT SVT = EVT::getVectorVT(*DAG.getContext(), SrcVT.getVectorElementType(),
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NumElems/2);
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SDValue SV1 = DAG.getVectorShuffle(SVT, dl, V1.getOperand(1),
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DAG.getUNDEF(SVT), &Mask[0]);
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SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), SV1,
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DAG.getConstant(0, MVT::i32), DAG, dl);
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return Insert128BitVector(InsV, SV1,
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DAG.getConstant(NumElems/2, MVT::i32), DAG, dl);
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}
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/// PromoteSplat - Promote a splat of v4i32, v8i16 or v16i8 to v4f32 and
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/// v8i32, v16i16 or v32i8 to v8f32.
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static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) {
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@ -5742,7 +5770,17 @@ SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG,
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if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI))
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return Op;
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// Handle splats by matching through known masks
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// Since there's no native support for scalar_to_vector for 256-bit AVX, a
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// 128-bit scalar_to_vector + INSERT_SUBVECTOR is generated. Recognize this
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// idiom and do the shuffle before the insertion, this yields less
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// instructions in the end.
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if (VT.is256BitVector() &&
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V1.getOpcode() == ISD::INSERT_SUBVECTOR &&
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V1.getOperand(0).getOpcode() == ISD::UNDEF &&
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V1.getOperand(1).getOpcode() == ISD::SCALAR_TO_VECTOR)
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return PromoteVectorToScalarSplat(SVOp, DAG);
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// Handle splats by matching through known shuffle masks
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if ((VT.is128BitVector() && NumElem <= 4) ||
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(VT.is256BitVector() && NumElem <= 8))
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return SDValue();
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@ -501,6 +501,9 @@ class RSDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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class RPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: PDI<o, F, outs, ins, asm, pattern>, REX_W;
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class VRPDI<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: VPDI<o, F, outs, ins, asm, pattern>, VEX_W;
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// MMX Instruction templates
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//
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@ -467,3 +467,4 @@ def vinsertf128_insert : PatFrag<(ops node:$bigvec, node:$smallvec,
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node:$index), [{
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return X86::isVINSERTF128Index(N);
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}], INSERT_get_vinsertf128_imm>;
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@ -2858,6 +2858,14 @@ def VMOVDI2PDIrm : VPDI<0x6E, MRMSrcMem, (outs VR128:$dst), (ins i32mem:$src),
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[(set VR128:$dst,
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(v4i32 (scalar_to_vector (loadi32 addr:$src))))]>,
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VEX;
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def VMOV64toPQIrr : VRPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
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"mov{d|q}\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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(v2i64 (scalar_to_vector GR64:$src)))]>, VEX;
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def VMOV64toSDrr : VRPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
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"mov{d|q}\t{$src, $dst|$dst, $src}",
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[(set FR64:$dst, (bitconvert GR64:$src))]>, VEX;
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def MOVDI2PDIrr : PDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR32:$src),
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"movd\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst,
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@ -5358,6 +5366,20 @@ def : Pat<(vinsertf128_insert:$ins (v16i16 VR256:$src1), (v8i16 VR128:$src2),
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(VINSERTF128rr VR256:$src1, VR128:$src2,
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(INSERT_get_vinsertf128_imm VR256:$ins))>;
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// Special COPY patterns
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def : Pat<(insert_subvector undef, (v2i64 VR128:$src), (i32 0)),
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(INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v2f64 VR128:$src), (i32 0)),
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(INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v4i32 VR128:$src), (i32 0)),
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(INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v4f32 VR128:$src), (i32 0)),
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(INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v8i16 VR128:$src), (i32 0)),
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(INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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def : Pat<(insert_subvector undef, (v16i8 VR128:$src), (i32 0)),
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(INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
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//===----------------------------------------------------------------------===//
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// VEXTRACTF128 - Extract packed floating-point values
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//
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@ -5,7 +5,6 @@
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; CHECK: vextractf128 $0
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; CHECK-NEXT: punpcklbw
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; CHECK-NEXT: punpckhbw
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; CHECK-NEXT: vinsertf128 $0
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; CHECK-NEXT: vinsertf128 $1
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; CHECK-NEXT: vpermilps $85
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define <32 x i8> @funcA(<32 x i8> %a) nounwind uwtable readnone ssp {
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@ -16,7 +15,6 @@ entry:
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; CHECK: vextractf128 $0
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; CHECK-NEXT: punpckhwd
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; CHECK-NEXT: vinsertf128 $0
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; CHECK-NEXT: vinsertf128 $1
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; CHECK-NEXT: vpermilps $85
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define <16 x i16> @funcB(<16 x i16> %a) nounwind uwtable readnone ssp {
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@ -25,3 +23,25 @@ entry:
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ret <16 x i16> %shuffle
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}
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; CHECK: vmovd
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; CHECK-NEXT: movlhps
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; CHECK-NEXT: vinsertf128 $1
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define <4 x i64> @funcC(i64 %q) nounwind uwtable readnone ssp {
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entry:
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%vecinit.i = insertelement <4 x i64> undef, i64 %q, i32 0
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%vecinit2.i = insertelement <4 x i64> %vecinit.i, i64 %q, i32 1
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%vecinit4.i = insertelement <4 x i64> %vecinit2.i, i64 %q, i32 2
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%vecinit6.i = insertelement <4 x i64> %vecinit4.i, i64 %q, i32 3
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ret <4 x i64> %vecinit6.i
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}
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; CHECK: vshufpd
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; CHECK-NEXT: vinsertf128 $1
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define <4 x double> @funcD(double %q) nounwind uwtable readnone ssp {
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entry:
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%vecinit.i = insertelement <4 x double> undef, double %q, i32 0
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%vecinit2.i = insertelement <4 x double> %vecinit.i, double %q, i32 1
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%vecinit4.i = insertelement <4 x double> %vecinit2.i, double %q, i32 2
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%vecinit6.i = insertelement <4 x double> %vecinit4.i, double %q, i32 3
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ret <4 x double> %vecinit6.i
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}
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@ -1,4 +1,4 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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@x = common global <8 x float> zeroinitializer, align 32
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@y = common global <4 x double> zeroinitializer, align 32
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@ -12,4 +12,3 @@ entry:
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store <4 x double> zeroinitializer, <4 x double>* @y, align 32
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ret void
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}
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