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[PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFC

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llvm-svn: 299303
This commit is contained in:
Sanjay Patel 2017-04-01 14:32:18 +00:00
parent d9dab6b15e
commit 939ff81f30
2 changed files with 237 additions and 0 deletions
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116
test/CodeGen/PowerPC/setcc-logic.ll
View File

@ -307,3 +307,119 @@ return:
ret i32 192
}
define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: all_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: xxlxor 36, 36, 36
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: vcmpequw 3, 3, 4
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: blr
%a = icmp eq <4 x i32> %P, zeroinitializer
%b = icmp eq <4 x i32> %Q, zeroinitializer
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: all_sign_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: vspltisb 4, -1
; CHECK-NEXT: vcmpgtsw 2, 2, 4
; CHECK-NEXT: vcmpgtsw 3, 3, 4
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: blr
%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: all_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: vspltisb 4, -1
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: vcmpequw 3, 3, 4
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: blr
%a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: all_sign_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: xxlxor 36, 36, 36
; CHECK-NEXT: vcmpgtsw 2, 4, 2
; CHECK-NEXT: vcmpgtsw 3, 4, 3
; CHECK-NEXT: xxland 34, 34, 35
; CHECK-NEXT: blr
%a = icmp slt <4 x i32> %P, zeroinitializer
%b = icmp slt <4 x i32> %Q, zeroinitializer
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: any_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: xxlxor 36, 36, 36
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: vcmpequw 3, 3, 4
; CHECK-NEXT: xxlnor 0, 34, 34
; CHECK-NEXT: xxlnor 1, 35, 35
; CHECK-NEXT: xxlor 34, 0, 1
; CHECK-NEXT: blr
%a = icmp ne <4 x i32> %P, zeroinitializer
%b = icmp ne <4 x i32> %Q, zeroinitializer
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: any_sign_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: xxlxor 36, 36, 36
; CHECK-NEXT: vcmpgtsw 2, 4, 2
; CHECK-NEXT: vcmpgtsw 3, 4, 3
; CHECK-NEXT: xxlor 34, 34, 35
; CHECK-NEXT: blr
%a = icmp slt <4 x i32> %P, zeroinitializer
%b = icmp slt <4 x i32> %Q, zeroinitializer
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: any_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: vspltisb 4, -1
; CHECK-NEXT: vcmpequw 2, 2, 4
; CHECK-NEXT: vcmpequw 3, 3, 4
; CHECK-NEXT: xxlnor 0, 34, 34
; CHECK-NEXT: xxlnor 1, 35, 35
; CHECK-NEXT: xxlor 34, 0, 1
; CHECK-NEXT: blr
%a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
; CHECK-LABEL: any_sign_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: vspltisb 4, -1
; CHECK-NEXT: vcmpgtsw 2, 2, 4
; CHECK-NEXT: vcmpgtsw 3, 3, 4
; CHECK-NEXT: xxlor 34, 34, 35
; CHECK-NEXT: blr
%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}

121
test/CodeGen/X86/setcc-logic.ll
View File

@ -313,6 +313,127 @@ return:
ret i32 192
}
define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: all_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: retq
%a = icmp eq <4 x i32> %P, zeroinitializer
%b = icmp eq <4 x i32> %Q, zeroinitializer
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: all_sign_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: retq
%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: all_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
; CHECK-NEXT: pand %xmm1, %xmm0
; CHECK-NEXT: retq
%a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: all_sign_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: pxor %xmm3, %xmm3
; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: pand %xmm3, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%a = icmp slt <4 x i32> %P, zeroinitializer
%b = icmp slt <4 x i32> %Q, zeroinitializer
%c = and <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: any_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
; CHECK-NEXT: pcmpeqd %xmm3, %xmm3
; CHECK-NEXT: pxor %xmm3, %xmm0
; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm3, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%a = icmp ne <4 x i32> %P, zeroinitializer
%b = icmp ne <4 x i32> %Q, zeroinitializer
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: any_sign_bits_set_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pxor %xmm2, %xmm2
; CHECK-NEXT: pxor %xmm3, %xmm3
; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
; CHECK-NEXT: por %xmm3, %xmm2
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
%a = icmp slt <4 x i32> %P, zeroinitializer
%b = icmp slt <4 x i32> %Q, zeroinitializer
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: any_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
; CHECK-NEXT: pxor %xmm2, %xmm0
; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
; CHECK-NEXT: pxor %xmm2, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
; CHECK-LABEL: any_sign_bits_clear_vec:
; CHECK: # BB#0:
; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
; CHECK-NEXT: por %xmm1, %xmm0
; CHECK-NEXT: retq
%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
%c = or <4 x i1> %a, %b
ret <4 x i1> %c
}
define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind {
; CHECK-LABEL: ne_neg1_and_ne_zero:
; CHECK: # BB#0: