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https://github.com/RPCS3/llvm-mirror.git
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[PowerPC, x86] add vector tests for any/all {sign} bits set/clear; NFC
llvm-svn: 299303
This commit is contained in:
parent
d9dab6b15e
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939ff81f30
@ -307,3 +307,119 @@ return:
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ret i32 192
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}
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define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: vcmpequw 3, 3, 4
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: blr
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%a = icmp eq <4 x i32> %P, zeroinitializer
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%b = icmp eq <4 x i32> %Q, zeroinitializer
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_sign_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: vcmpgtsw 2, 2, 4
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; CHECK-NEXT: vcmpgtsw 3, 3, 4
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: blr
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%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: vcmpequw 3, 3, 4
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: blr
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%a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: all_sign_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: vcmpgtsw 2, 4, 2
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; CHECK-NEXT: vcmpgtsw 3, 4, 3
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; CHECK-NEXT: xxland 34, 34, 35
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; CHECK-NEXT: blr
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%a = icmp slt <4 x i32> %P, zeroinitializer
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%b = icmp slt <4 x i32> %Q, zeroinitializer
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: vcmpequw 3, 3, 4
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; CHECK-NEXT: xxlnor 0, 34, 34
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; CHECK-NEXT: xxlnor 1, 35, 35
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; CHECK-NEXT: xxlor 34, 0, 1
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; CHECK-NEXT: blr
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%a = icmp ne <4 x i32> %P, zeroinitializer
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%b = icmp ne <4 x i32> %Q, zeroinitializer
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_sign_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: xxlxor 36, 36, 36
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; CHECK-NEXT: vcmpgtsw 2, 4, 2
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; CHECK-NEXT: vcmpgtsw 3, 4, 3
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; CHECK-NEXT: xxlor 34, 34, 35
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; CHECK-NEXT: blr
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%a = icmp slt <4 x i32> %P, zeroinitializer
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%b = icmp slt <4 x i32> %Q, zeroinitializer
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: vcmpequw 2, 2, 4
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; CHECK-NEXT: vcmpequw 3, 3, 4
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; CHECK-NEXT: xxlnor 0, 34, 34
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; CHECK-NEXT: xxlnor 1, 35, 35
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; CHECK-NEXT: xxlor 34, 0, 1
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; CHECK-NEXT: blr
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%a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) {
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; CHECK-LABEL: any_sign_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: vspltisb 4, -1
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; CHECK-NEXT: vcmpgtsw 2, 2, 4
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; CHECK-NEXT: vcmpgtsw 3, 3, 4
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; CHECK-NEXT: xxlor 34, 34, 35
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; CHECK-NEXT: blr
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%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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@ -313,6 +313,127 @@ return:
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ret i32 192
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}
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define <4 x i1> @all_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: all_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: retq
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%a = icmp eq <4 x i32> %P, zeroinitializer
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%b = icmp eq <4 x i32> %Q, zeroinitializer
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: all_sign_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
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; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
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; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: retq
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%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: all_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
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; CHECK-NEXT: pand %xmm1, %xmm0
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; CHECK-NEXT: retq
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%a = icmp eq <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp eq <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @all_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: all_sign_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: pxor %xmm3, %xmm3
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; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
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; CHECK-NEXT: pand %xmm3, %xmm2
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; CHECK-NEXT: movdqa %xmm2, %xmm0
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; CHECK-NEXT: retq
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%a = icmp slt <4 x i32> %P, zeroinitializer
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%b = icmp slt <4 x i32> %Q, zeroinitializer
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%c = and <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: any_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
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; CHECK-NEXT: pcmpeqd %xmm3, %xmm3
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; CHECK-NEXT: pxor %xmm3, %xmm0
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
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; CHECK-NEXT: pxor %xmm3, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%a = icmp ne <4 x i32> %P, zeroinitializer
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%b = icmp ne <4 x i32> %Q, zeroinitializer
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_sign_bits_set_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: any_sign_bits_set_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pxor %xmm2, %xmm2
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; CHECK-NEXT: pxor %xmm3, %xmm3
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; CHECK-NEXT: pcmpgtd %xmm0, %xmm3
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; CHECK-NEXT: pcmpgtd %xmm1, %xmm2
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; CHECK-NEXT: por %xmm3, %xmm2
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; CHECK-NEXT: movdqa %xmm2, %xmm0
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; CHECK-NEXT: retq
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%a = icmp slt <4 x i32> %P, zeroinitializer
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%b = icmp slt <4 x i32> %Q, zeroinitializer
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: any_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm0
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; CHECK-NEXT: pxor %xmm2, %xmm0
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm1
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; CHECK-NEXT: pxor %xmm2, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%a = icmp ne <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp ne <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define <4 x i1> @any_sign_bits_clear_vec(<4 x i32> %P, <4 x i32> %Q) nounwind {
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; CHECK-LABEL: any_sign_bits_clear_vec:
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; CHECK: # BB#0:
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; CHECK-NEXT: pcmpeqd %xmm2, %xmm2
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; CHECK-NEXT: pcmpgtd %xmm2, %xmm0
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; CHECK-NEXT: pcmpgtd %xmm2, %xmm1
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; CHECK-NEXT: por %xmm1, %xmm0
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; CHECK-NEXT: retq
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%a = icmp sgt <4 x i32> %P, <i32 -1, i32 -1, i32 -1, i32 -1>
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%b = icmp sgt <4 x i32> %Q, <i32 -1, i32 -1, i32 -1, i32 -1>
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%c = or <4 x i1> %a, %b
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ret <4 x i1> %c
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}
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define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind {
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; CHECK-LABEL: ne_neg1_and_ne_zero:
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; CHECK: # BB#0:
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