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[Thumb1] Re-write emitThumbRegPlusImmediate
This was motivated by a bug which caused code like this to be
miscompiled:
declare void @take_ptr(i8*)
define void @test() {
%addr1.32 = alloca i8
%addr2.32 = alloca i32, i32 1028
call void @take_ptr(i8* %addr1)
ret void
}
This was emitting the following assembly to get the value of %addr1:
add r0, sp, #1020
add r0, r0, #8
However, "add r0, r0, #8" is not a valid Thumb1 instruction, and this
could not be assembled. The generated object file contained this,
resulting in r0 holding SP+8 rather tha SP+1028:
add r0, sp, #1020
add r0, sp, #8
This function looked like it could have caused miscompilations for
other combinations of registers and offsets (though I don't think it is
currently called with these), and the heuristic it used did not match
the emitted code in all cases.
llvm-svn: 222125
This commit is contained in:
Oliver Stannard
parent
903d9c0ab0
commit
93a823bc7a
@ -595,10 +595,10 @@ inline uint64_t PowerOf2Floor(uint64_t A) {
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/// RoundUpToAlignment(5, 8) = 8
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/// RoundUpToAlignment(17, 8) = 24
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/// RoundUpToAlignment(~0LL, 8) = 0
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/// RoundUpToAlignment(321, 255) = 510
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/// \endcode
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inline uint64_t RoundUpToAlignment(uint64_t Value, uint64_t Align) {
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assert(isPowerOf2_64(Align) && "Alignment must be power of 2!");
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return (Value + Align - 1) & ~uint64_t(Align - 1);
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return (Value + Align - 1) / Align * Align;
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}
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/// Returns the offset to the next integer (mod 2**64) that is greater than
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@ -66,6 +66,10 @@ Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
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int Val,
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ARMCC::CondCodes Pred, unsigned PredReg,
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unsigned MIFlags) const {
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assert((isARMLowRegister(DestReg) ||
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isVirtualRegister(DestReg)) &&
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"Thumb1 does not have ldr to high register");
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MachineFunction &MF = *MBB.getParent();
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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MachineConstantPool *ConstantPool = MF.getConstantPool();
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@ -106,15 +110,15 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
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NumBytes = -NumBytes;
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}
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unsigned LdReg = DestReg;
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if (DestReg == ARM::SP) {
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if (DestReg == ARM::SP)
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assert(BaseReg == ARM::SP && "Unexpected!");
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if (!isARMLowRegister(DestReg) && !MRI.isVirtualRegister(DestReg))
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LdReg = MF.getRegInfo().createVirtualRegister(&ARM::tGPRRegClass);
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}
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if (NumBytes <= 255 && NumBytes >= 0)
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if (NumBytes <= 255 && NumBytes >= 0 && CanChangeCC) {
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
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.addImm(NumBytes).setMIFlags(MIFlags);
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else if (NumBytes < 0 && NumBytes >= -255) {
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} else if (NumBytes < 0 && NumBytes >= -255 && CanChangeCC) {
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg))
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.addImm(NumBytes).setMIFlags(MIFlags);
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg))
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@ -124,7 +128,8 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
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ARMCC::AL, 0, MIFlags);
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// Emit add / sub.
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int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
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int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
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: ARM::tADDrr);
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MachineInstrBuilder MIB =
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BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (Opc != ARM::tADDhirr)
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@ -136,32 +141,10 @@ void emitThumbRegPlusImmInReg(MachineBasicBlock &MBB,
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AddDefaultPred(MIB);
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}
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/// calcNumMI - Returns the number of instructions required to materialize
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/// the specific add / sub r, c instruction.
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static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes,
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unsigned NumBits, unsigned Scale) {
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unsigned NumMIs = 0;
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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if (Opc == ARM::tADDrSPi) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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NumMIs++;
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NumBits = 8;
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Scale = 1; // Followed by a number of tADDi8.
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Chunk = ((1 << NumBits) - 1) * Scale;
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}
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NumMIs += Bytes / Chunk;
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if ((Bytes % Chunk) != 0)
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NumMIs++;
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if (ExtraOpc)
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NumMIs++;
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return NumMIs;
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}
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/// emitThumbRegPlusImmediate - Emits a series of instructions to materialize
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/// a destreg = basereg + immediate in Thumb code.
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/// a destreg = basereg + immediate in Thumb code. Tries a series of ADDs or
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/// SUBs first, and uses a constant pool value if the instruction sequence would
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/// be too long. This is allowed to modify the condition flags.
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void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &MBBI,
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DebugLoc dl,
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@ -172,131 +155,146 @@ void llvm::emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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bool isSub = NumBytes < 0;
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unsigned Bytes = (unsigned)NumBytes;
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if (isSub) Bytes = -NumBytes;
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bool isMul4 = (Bytes & 3) == 0;
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bool isTwoAddr = false;
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bool DstNotEqBase = false;
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unsigned NumBits = 1;
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unsigned Scale = 1;
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int Opc = 0;
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int ExtraOpc = 0;
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bool NeedCC = false;
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if (DestReg == BaseReg && BaseReg == ARM::SP) {
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assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
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NumBits = 7;
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Scale = 4;
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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isTwoAddr = true;
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} else if (!isSub && BaseReg == ARM::SP) {
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// r1 = add sp, 403
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// =>
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// r1 = add sp, 100 * 4
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// r1 = add r1, 3
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if (!isMul4) {
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Bytes &= ~3;
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ExtraOpc = ARM::tADDi3;
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}
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DstNotEqBase = true;
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NumBits = 8;
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Scale = 4;
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Opc = ARM::tADDrSPi;
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} else {
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// sp = sub sp, c
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// r1 = sub sp, c
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// r8 = sub sp, c
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if (DestReg != BaseReg)
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DstNotEqBase = true;
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if (DestReg == ARM::SP) {
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Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
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NumBits = 7;
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Scale = 4;
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int CopyOpc = 0;
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unsigned CopyBits = 0;
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unsigned CopyScale = 1;
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bool CopyNeedsCC = false;
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int ExtraOpc = 0;
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unsigned ExtraBits = 0;
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unsigned ExtraScale = 1;
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bool ExtraNeedsCC = false;
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// Strategy:
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// We need to select two types of instruction, maximizing the available
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// immediate range of each. The instructions we use will depend on whether
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// DestReg and BaseReg are low, high or the stack pointer.
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// * CopyOpc - DestReg = BaseReg + imm
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// This will be emitted once if DestReg != BaseReg, and never if
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// DestReg == BaseReg.
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// * ExtraOpc - DestReg = DestReg + imm
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// This will be emitted as many times as necessary to add the
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// full immediate.
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// If the immediate ranges of these instructions are not large enough to cover
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// NumBytes with a reasonable number of instructions, we fall back to using a
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// value loaded from a constant pool.
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if (DestReg == ARM::SP) {
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if (BaseReg == ARM::SP) {
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// sp -> sp
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// Already in right reg, no copy needed
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} else {
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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NumBits = 8;
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NeedCC = true;
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// low -> sp or high -> sp
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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}
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isTwoAddr = true;
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ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
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ExtraBits = 7;
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ExtraScale = 4;
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} else if (isARMLowRegister(DestReg)) {
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if (BaseReg == ARM::SP) {
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// sp -> low
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assert(!isSub && "Thumb1 does not have tSUBrSPi");
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CopyOpc = ARM::tADDrSPi;
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CopyBits = 8;
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CopyScale = 4;
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} else if (DestReg == BaseReg) {
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// low -> same low
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// Already in right reg, no copy needed
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} else if (isARMLowRegister(BaseReg)) {
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// low -> different low
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CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
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CopyBits = 3;
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CopyNeedsCC = true;
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} else {
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// high -> low
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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}
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ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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ExtraBits = 8;
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ExtraNeedsCC = true;
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} else /* DestReg is high */ {
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if (DestReg == BaseReg) {
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// high -> same high
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// Already in right reg, no copy needed
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} else {
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// {low,high,sp} -> high
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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}
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ExtraOpc = 0;
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}
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unsigned NumMIs = calcNumMI(Opc, ExtraOpc, Bytes, NumBits, Scale);
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// We could handle an unaligned immediate with an unaligned copy instruction
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// and an aligned extra instruction, but this case is not currently needed.
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assert(((Bytes & 3) == 0 || ExtraScale == 1) &&
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"Unaligned offset, but all instructions require alignment");
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unsigned CopyRange = ((1 << CopyBits) - 1) * CopyScale;
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// If we would emit the copy with an immediate of 0, just use tMOVr.
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if (CopyOpc && Bytes < CopyScale) {
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CopyOpc = ARM::tMOVr;
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CopyBits = 0;
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CopyScale = 1;
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CopyNeedsCC = false;
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CopyRange = 0;
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}
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unsigned ExtraRange = ((1 << ExtraBits) - 1) * ExtraScale; // per instruction
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unsigned RequiredCopyInstrs = CopyOpc ? 1 : 0;
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unsigned RangeAfterCopy = (CopyRange > Bytes) ? 0 : (Bytes - CopyRange);
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// We could handle this case when the copy instruction does not require an
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// aligned immediate, but we do not currently do this.
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assert(RangeAfterCopy % ExtraScale == 0 &&
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"Extra instruction requires immediate to be aligned");
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unsigned RequiredExtraInstrs;
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if (ExtraRange)
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RequiredExtraInstrs = RoundUpToAlignment(RangeAfterCopy, ExtraRange) / ExtraRange;
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else if (RangeAfterCopy > 0)
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// We need an extra instruction but none is available
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RequiredExtraInstrs = 1000000;
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else
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RequiredExtraInstrs = 0;
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unsigned RequiredInstrs = RequiredCopyInstrs + RequiredExtraInstrs;
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unsigned Threshold = (DestReg == ARM::SP) ? 3 : 2;
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if (NumMIs > Threshold) {
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// This will expand into too many instructions. Load the immediate from a
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// constpool entry.
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// Use a constant pool, if the sequence of ADDs/SUBs is too expensive.
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if (RequiredInstrs > Threshold) {
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emitThumbRegPlusImmInReg(MBB, MBBI, dl,
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DestReg, BaseReg, NumBytes, true,
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TII, MRI, MIFlags);
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return;
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}
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if (DstNotEqBase) {
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if (isARMLowRegister(DestReg) && isARMLowRegister(BaseReg)) {
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// If both are low registers, emit DestReg = add BaseReg, max(Imm, 7)
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unsigned Chunk = (1 << 3) - 1;
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3);
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const MachineInstrBuilder MIB =
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AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)
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.setMIFlags(MIFlags));
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AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
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} else if (isARMLowRegister(DestReg) && BaseReg == ARM::SP && Bytes > 0) {
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unsigned ThisVal = std::min(1020U, Bytes / 4 * 4);
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Bytes -= ThisVal;
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), DestReg)
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.addReg(BaseReg, RegState::Kill).addImm(ThisVal / 4))
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.setMIFlags(MIFlags);
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} else {
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AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
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.addReg(BaseReg, RegState::Kill))
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.setMIFlags(MIFlags);
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// Emit zero or one copy instructions
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if (CopyOpc) {
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unsigned CopyImm = std::min(Bytes, CopyRange) / CopyScale;
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Bytes -= CopyImm * CopyScale;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
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if (CopyNeedsCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(BaseReg, RegState::Kill);
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if (CopyOpc != ARM::tMOVr) {
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MIB.addImm(CopyImm);
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}
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AddDefaultPred(MIB.setMIFlags(MIFlags));
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BaseReg = DestReg;
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}
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unsigned Chunk = ((1 << NumBits) - 1) * Scale;
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// Emit zero or more in-place add/sub instructions
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while (Bytes) {
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unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes;
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Bytes -= ThisVal;
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ThisVal /= Scale;
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// Build the new tADD / tSUB.
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if (isTwoAddr) {
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (NeedCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(DestReg).addImm(ThisVal);
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MIB = AddDefaultPred(MIB);
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MIB.setMIFlags(MIFlags);
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} else {
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bool isKill = BaseReg != ARM::SP;
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
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if (NeedCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(BaseReg, getKillRegState(isKill)).addImm(ThisVal);
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MIB = AddDefaultPred(MIB);
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MIB.setMIFlags(MIFlags);
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unsigned ExtraImm = std::min(Bytes, ExtraRange) / ExtraScale;
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Bytes -= ExtraImm * ExtraScale;
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BaseReg = DestReg;
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if (Opc == ARM::tADDrSPi) {
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// r4 = add sp, imm
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// r4 = add r4, imm
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// ...
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NumBits = 8;
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Scale = 1;
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Chunk = ((1 << NumBits) - 1) * Scale;
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Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
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NeedCC = isTwoAddr = true;
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}
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}
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}
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if (ExtraOpc) {
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const MCInstrDesc &MCID = TII.get(ExtraOpc);
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AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg))
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.addReg(DestReg, RegState::Kill)
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.addImm(((unsigned)NumBytes) & 3)
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.setMIFlags(MIFlags));
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MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
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if (ExtraNeedsCC)
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MIB = AddDefaultT1CC(MIB);
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MIB.addReg(BaseReg).addImm(ExtraImm);
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MIB = AddDefaultPred(MIB);
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MIB.setMIFlags(MIFlags);
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}
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}
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@ -1,5 +1,7 @@
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
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; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-darwin
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; RUN: llvm-objdump -triple=thumbv6-apple-darwin -d %t | FileCheck %s
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@__bar = external hidden global i8*
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@__baz = external hidden global i8*
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@ -49,13 +51,13 @@ define void @test_local_var_addr() {
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%addr2 = alloca i8
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; CHECK: mov r0, sp
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; CHECK: adds r0, r0, #{{[0-9]+}}
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; CHECK: blx _take_ptr
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; CHECK: adds r0, #{{[0-9]+}}
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; CHECK: blx
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call void @take_ptr(i8* %addr1)
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; CHECK: mov r0, sp
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; CHECK: adds r0, r0, #{{[0-9]+}}
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; CHECK: blx _take_ptr
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; CHECK: adds r0, #{{[0-9]+}}
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; CHECK: blx
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call void @take_ptr(i8* %addr2)
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ret void
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@ -70,7 +72,7 @@ define void @test_simple_var() {
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; CHECK: mov r0, sp
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; CHECK-NOT: adds r0
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; CHECK: blx _take_ptr
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; CHECK: blx
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call void @take_ptr(i8* %addr8)
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ret void
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}
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@ -85,12 +87,12 @@ define void @test_local_var_addr_aligned() {
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%addr2 = bitcast i32* %addr2.32 to i8*
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; CHECK: add r0, sp, #{{[0-9]+}}
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; CHECK: blx _take_ptr
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; CHECK: blx
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call void @take_ptr(i8* %addr1)
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; CHECK: mov r0, sp
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; CHECK-NOT: add r0
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; CHECK: blx _take_ptr
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; CHECK: blx
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call void @take_ptr(i8* %addr2)
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ret void
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@ -104,8 +106,35 @@ define void @test_local_var_big_offset() {
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%addr2.32 = alloca i32, i32 257
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; CHECK: add [[RTMP:r[0-9]+]], sp, #1020
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; CHECL: add r0, [[RTMP]], #8
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; CHECK: blx _take_ptr
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; CHECK: adds [[RTMP]], #8
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; CHECK: blx
|
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call void @take_ptr(i8* %addr1)
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Max range addressable with tADDrSPi
|
||||
define void @test_local_var_offset_1020() {
|
||||
; CHECK-LABEL: test_local_var_offset_1020
|
||||
%addr1 = alloca i8, i32 4
|
||||
%addr2 = alloca i8, i32 1020
|
||||
|
||||
; CHECK: add r0, sp, #1020
|
||||
; CHECK-NEXT: blx
|
||||
call void @take_ptr(i8* %addr1)
|
||||
|
||||
ret void
|
||||
}
|
||||
|
||||
; Max range addressable with tADDrSPi + tADDi8
|
||||
define void @test_local_var_offset_1275() {
|
||||
; CHECK-LABEL: test_local_var_offset_1275
|
||||
%addr1 = alloca i8, i32 1
|
||||
%addr2 = alloca i8, i32 1275
|
||||
|
||||
; CHECK: add r0, sp, #1020
|
||||
; CHECK: adds r0, #255
|
||||
; CHECK-NEXT: blx
|
||||
call void @take_ptr(i8* %addr1)
|
||||
|
||||
ret void
|
||||
|
||||
@ -1,31 +1,57 @@
|
||||
; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s
|
||||
; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s --check-prefix=CHECK --check-prefix=IOS
|
||||
; RUN: llc < %s -mtriple=thumb-none-eabi | FileCheck %s --check-prefix=CHECK --check-prefix=EABI
|
||||
; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-apple-ios
|
||||
; RUN: llvm-objdump -triple=thumbv6-apple-ios -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=IOS
|
||||
; RUN: llc < %s -o %t -filetype=obj -mtriple=thumbv6-none-eabi
|
||||
; RUN: llvm-objdump -triple=thumbv6-none-eabi -d %t | FileCheck %s --check-prefix=CHECK --check-prefix=EABI
|
||||
|
||||
; Largest stack for which a single tADDspi/tSUBspi is enough
|
||||
define void @test1() {
|
||||
; CHECK-LABEL: test1:
|
||||
; CHECK: sub sp, #256
|
||||
; CHECK: add sp, #256
|
||||
%tmp = alloca [ 64 x i32 ] , align 4
|
||||
; CHECK: sub sp, #508
|
||||
; CHECK: add sp, #508
|
||||
%tmp = alloca [ 508 x i8 ] , align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Largest stack for which three tADDspi/tSUBspis are enough
|
||||
define void @test100() {
|
||||
; CHECK-LABEL: test100:
|
||||
; CHECK: sub sp, #508
|
||||
; CHECK: sub sp, #508
|
||||
; CHECK: sub sp, #508
|
||||
; EABI: add sp, #508
|
||||
; EABI: add sp, #508
|
||||
; EABI: add sp, #508
|
||||
; IOS: subs r4, r7, #4
|
||||
; IOS: mov sp, r4
|
||||
%tmp = alloca [ 1524 x i8 ] , align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
; Smallest stack for which we use a constant pool
|
||||
define void @test2() {
|
||||
; CHECK-LABEL: test2:
|
||||
; CHECK: ldr r0, LCPI
|
||||
; CHECK: ldr r0,
|
||||
; CHECK: add sp, r0
|
||||
; CHECK: subs r4, r7, #4
|
||||
; CHECK: mov sp, r4
|
||||
%tmp = alloca [ 4168 x i8 ] , align 4
|
||||
; EABI: ldr r0,
|
||||
; EABI: add sp, r0
|
||||
; IOS: subs r4, r7, #4
|
||||
; IOS: mov sp, r4
|
||||
%tmp = alloca [ 1528 x i8 ] , align 4
|
||||
ret void
|
||||
}
|
||||
|
||||
define i32 @test3() {
|
||||
; CHECK-LABEL: test3:
|
||||
; CHECK: ldr r1, LCPI
|
||||
; CHECK: ldr r1,
|
||||
; CHECK: add sp, r1
|
||||
; CHECK: ldr r1, LCPI
|
||||
; CHECK: ldr r1,
|
||||
; CHECK: add r1, sp
|
||||
; CHECK: subs r4, r7, #4
|
||||
; CHECK: mov sp, r4
|
||||
; EABI: ldr r1,
|
||||
; EABI: add sp, r1
|
||||
; IOS: subs r4, r7, #4
|
||||
; IOS: mov sp, r4
|
||||
%retval = alloca i32, align 4
|
||||
%tmp = alloca i32, align 4
|
||||
%a = alloca [805306369 x i8], align 16
|
||||
|
||||
Loading…
Reference in New Issue
Block a user